82371AB Datasheet, PDF (104/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Bit
Description
11 Signaled Target-Abort Status (STA)—R/WC. This bit is set when the Serial Bus module function is
targeted with a transaction that the Serial Bus module terminates with a target abort. Software resets
STA to 0 by writing a 1 to this bit.
10:9 DEVSEL# Timing Status (DEVT)—RO. This 2-bit field defines the timing for DEVSEL# assertion.
These read only bits indicate PIIX4’s DEVSEL# timing when performing a positive decode. Since
PIIX4 always generate the DEVSEL# with medium timing, DEVT=01. This DEVSEL# timing does not
include Configuration cycles.
8 Data Parity Detected (Not Implemented). Read as 0.
7 Fast Back to Back Capable (FBC)—RO. Hardwired to 1. This bit indicates to the PCI Master that
Serial Bus module as a target is capable of accepting fast back-to-back transactions.
6:0 Reserved. Read as 0’s.
6.1.5. RID—REVISION IDENTIFICATION REGISTER (FUNCTION 2)
Address Offset:
Default Value:
Attribute:
08h
Initial Stepping=00h. Refer to PIIX4 Specification Updates for other values
programmed here.
Read Only
This 8-bit register contains device stepping information. Writes to this register have no effect.
Bit
Description
7:0 Revision ID Byte. The register is hardwired to the default value.
6.1.6. CLASSC—CLASS CODE REGISTER (FUNCTION 2)
Address Offset:
Default Value:
Attribute:
09−0Bh
0C0300h
Read Only
This register identifies the Base Class Code, Sub Class Code, and Device Programming interface for PIIX4 PCI
function 2.
Bit
Description
23:16 Base Class Code (BASEC). 0Ch=Serial Bus controller.
15:8 Sub Class Code (SCC). 03h=Universal Serial Bus Host Controller.
7:0 Programming Interface (PI). 00h=Universal Host Controller Interface.
104
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4/9/97 2:23 PM PIIX4aDS
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