82371AB Datasheet, PDF (66/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Bit
Description
16 SERIRQ/GPI7 Signal Pin Select. 0=GPI7 (default). 1=SERIRQ signal. This bit selects the
functionality multiplexed onto the SERIRQ pin.
15 SMBALERT#/GPI11 Signal Pin Select. 0=SMBALERT# signal (default). 1=GPI11. This bit selects
the functionality multiplexed onto the SMBALERT# pin.
14 IRQ8#/GPI6 Signal Pin Select. 0=GPI6 (default). 1=IRQ8# signal. This bit selects the functionality
multiplexed onto the IRQ8# pin.
13 Reserved.
12 Secondary IDE Signal Interface Tri-State. 0=Enable Secondary IDE signal pin interface (default).
1=Tri-state (disable) Secondary IDE signal pin interface. This bit functions independently of bit 4.
11 Primary IDE Signal Interface Tri-State. 0=Enable Primary IDE signal pin interface (default). 1=Tri-
state (disable) Primary IDE signal pin interface. This bit functions independently of bit 4.
10 PC/PCI REQ[C] and GNT[C]/GPI4 and GPO11 Signal Pin Select. 0=GPI4 and GPO11 (default).
1=PC/PCI REQC and GNTC respectively. This bit selects the functionality multiplexed onto the
REQC and GNTC pins.
9 PC/PCI REQ[B] and GNTB/GPI3 and GPO10 Signal Pin Select. 0=GPI3 and GPO10 (default).
1=PC/PCI REQB and GNTB respectively. This bit selects the functionality multiplexed onto the
REQB and GNTB pins.
8 PC/PCI REQA and GNTA/GPI2 and GPO9 Signal Pin Select. 0=GPI2 and GPO9 (default).
1=PC/PCI REQA and GNTA respectively. This bit selects the functionality multiplexed onto the
REQA and GNTA pins.
7 Reserved.
6 Plug and Play (PnP) Address Decode Enable. 0=Disable PnP address positive decode (default).
1=Enable PnP address positive decode and forwarding to the ISA bus. The PnP addresses which
are decoded are 279h and A79h. If bit 1 is set for positive decode, this bit must be set for these
address to be forwarded to ISA.
5 Alternate Access Mode Enable. 0=Disable Alternate Access Mode (default). 1=Enables Alternate
Access Mode to allow access to shadow registers as described in the Power Management
Functional Description section. Enabling this bit allows special access to various internal PIIX4
registers. See special access restrictions prior to setting this bit.
4 IDE Signal Configuration. 0=Primary and Secondary interface enable (default). 1=Primary 0 and
Primary 1 interface enable. This bit selects whether the IDE interfaces are split for Primary and
Secondary channels allowing access to 4 IDE devices or are split into Primary Drive 0 and Primary
Drive 1 channels allowing access to only the two Primary IDE devices.
3 CONFIG 2 Status (RO). This bit provides indication of signal present on CONFIG2 pin. Its meaning
is currently undefined. The use of this pin is RESERVED and should be tied low through a pull down
resistor.
2 CONFIG 1 Status (RO). 0=Pentium processor. 1=Pentium II processor. This bit provides indication
of signal present on CONFIG1 pin. It is used to change the polarity of the INIT and CPURST signals
to match the requirements of the microprocessors.
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PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)