82371AB Datasheet, PDF (88/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
4.2.7.4.
RC—Reset Control Register (IO)
I/O Address:
Default Value:
Attribute:
CF9h
00h
Read/Write
Bits 1 and 2 in this register are used by PIIX4 to generate a hard reset or a soft reset. During a hard reset, PIIX4
asserts CPURST, PCIRST#, and RSTDRV, as well as reset its core and suspend well logic. During
a soft reset, PIIX4 asserts INIT.
Bit
Description
7:3 Reserved.
2 Reset CPU (RCPU). This bit is used to initiate (transitions from 0 to 1) a hard reset (bit 1 in this
register is set to 1) or a soft reset to the CPU. PIIX4 will also initiate a hard reset when PWROK is
asserted. This bit cannot be read as a 1.
1 System Reset (SRST). This bit is used to select the type of reset generated when bit 2 in this
register is set to 1. When SRST=1, PIIX4 initiates a hard reset to the CPU when bit 2 in this register
transitions from 0 to 1. When SRST=0, PIIX4 initiates a soft reset when bit 2 in this register
transitions from 0 to 1.
0 Reserved.
88
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)