82371AB Datasheet, PDF (152/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
7.3.8. SMBBLKDAT—SMBUS BLOCK DATA REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (07h)
00h
Read/Write
Reads and writes to this register are used to access the 32-byte block data storage array. An internal index
pointer is used to address the array. It is reset to 0 by reading the SMBHSTCNT register. The index pointer then
increments automatically upon each access to this register. The transfer of block data into (read) or out of (write)
this storage array during an SMBus transaction always starts at index address 0.
Bit
Description
7:0 SMBus Block Data (BLK_DAT)—R/W. This register is used to transfer data into or out of the block
data storage array.
7.3.9. SMBSLVCNT—SMBUS SLAVE CONTROL REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (08h)
00h
Read/Write
The control register is used to enable SMBus controller slave interface functions.
Bit
Description
7:4 Reserved.
3 SMBus Alert Enable (ALERT_EN)—R/W. 1=Enable the generation of an interrupt or resume event
on the assertion of SMBALERT# signal. 0=Disable.
2 SMBus Shadow Port 2 Enable (SHDW2_EN)—R/W. 1=Enable the generation of an interrupt or
resume event upon an external SMBus master generating a transaction with an address that
matches the SMBSHDW2 register. 0=Disable.
1 SMBus Shadow Port 1 Enable (SHDW1_EN)—R/W. 1=Enable the generation of an interrupt or
resume event upon an external SMBus master generating a transaction with an address that
matches the SMBSHDW1 register. 0=Disable.
0 Slave Enable (SLV_EN)—R/W. 1=Enable the generation of an interrupt or resume event upon an
external SMBus master generating a transaction with an address that matches the host controller
slave port of 10h, a command field which matches the SMBSLVC register, and a match of one of the
corresponding enabled events in the SMBSLVEVT register. 0=Disable.
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