82371AB Datasheet, PDF (202/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
into a power managed condition (such as Local Standby or Powered Off). Accesses targeting that device are
then monitored. When detected, an SMI# is generated to allow the software to restore the device to
operation.
• 14 distinct device monitors and idle timers for various system devices
• Four generic device monitors
• Can monitor devices on PCI or ISA bus
• Can monitor General Purpose Inputs
• I/O SMI# traps with I/O cycle restart timing
• Device address ranges can be used to forward cycles to ISA bus
System Management: In addition to individual devices, PIIX4 provides capabilities to monitor other events
within the system, including an external power button, notebook lid or other type of switch, global system activity,
thermal alarm input, countdown timers, and SMBus message generation and receipt. These events can generate
an SMI to the processor allowing the software to manage system as necessary.
System Suspend: Once the power management software has determined that the system is fully idle or that a
critical system event has occurred, it can place the system into a suspend state, which allows for increased
power savings. The software configures PIIX4 for the type of suspend, types of resume or wake-up events, and
then PIIX4 automatically transitions the system into suspend. When an enabled resume event is detected, PIIX4
automatically restores the system to operation.
• Three suspend states
• Power-on-Suspend (POS) with three system reset options
• Suspend-to-RAM (STR)
• Suspend-to-Disk (STD) or Soff Off (SOff)
• Global Standby Timer (also active during suspend) to monitor for overall system idleness and as
a resume timer
• Power Button Input (PWRBTN#)
• Override feature forcing immediate transition to Soft Off
• Battery Low indication pin (BATLOW#)
• Shadow registers for standard AT write only registers to save and restore system state information
• “Resume Well” to monitor wake-up events during suspend
• Resume power and reset sequencing
11.2. Clock Control
PIIX4 provides the ability to separately control the system Host clocks and PCI clocks. The Host Clock Control
primarily uses the processor clock control features, but adds unique capabilities to allow for more flexible and
robust power management. It supports both the Pentium processor Stop Grant and Stop Clock states, as well as
the Pentium II processor Stop Grant and Sleep states or Quick Start and Deep Sleep states. The PCI Clock
Control follows the Clock Run mechanism as described in the PCI Mobile Design Guide. An example system
configuration is shown in Figure 10.
11.2.1. HOST CLOCK CONTROL MECHANISMS
PIIX4 support four primary Host Clock Control Mechanisms, with three types of variations. System events can
be monitored to break out of clock control modes or to generate burst execution. Software enables clock control
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