82371AB Datasheet, PDF (175/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
The Poll command is issued by setting P=1 in OCW3. The Interrupt Controller treats the next I/O read pulse to
the Interrupt Controller as an interrupt acknowledge, sets the appropriate IS bit if there is a request, and reads
the priority level. Interrupts are frozen from the I/O write to the I/O read.
This mode is useful if there is a routine command common to several levels so that the INTA# sequence is not
needed (saves ROM space).
8.6.4. CASCADE MODE
The Interrupt Controllers in PIIX4 are interconnected in a cascade configuration with one master and one slave.
This configuration can handle up to 15 separate priority levels.
The master controls the slaves through a three line internal cascade bus. When the master drives 010b on the
cascade bus, this bus acts like a chip select to the slave controller.
In a cascade configuration, the slave interrupt outputs are connected to the master interrupt request inputs.
When a slave request line is activated and afterwards acknowledged, the master enables the corresponding
slave to release the interrupt vector address during the second INTA# cycle of the interrupt acknowledge
sequence.
Each Interrupt Controller in the cascaded system must follow a separate initialization sequence and can be
programmed to work in a different mode. An EOI Command must be issued twice: once for the master and once
for the slave.
8.6.5. EDGE AND LEVEL TRIGGERED MODE
In ISA systems this mode is programmed using bit 3 in ICW1. With PIIX4, this bit is disabled and a new register
for edge and level triggered mode selection, per interrupt input, is included. This is the Edge/Level control
Registers ELCR1 and ELCR2. The default programming is equivalent to programming the LTIM bit (ICW1 bit 3)
to a 0 (all interrupts selected for edge triggered mode). Note, that IRQ0, 1, 2, 8#, and 13 can not be programmed
for level sensitive mode and can not be modified by software.
If an ELCR bit=0, an interrupt request is recognized by a low to high transition on the corresponding IRQx input.
The IRQ input can remain high without generating another interrupt.
If an ELCR bit=1, an interrupt request is recognized by a high level on the corresponding IRQ input and there is
no need for an edge detection. The interrupt request must be removed before the EOI command is issued to
prevent a second interrupt from occurring.
In both the edge and level triggered modes, the IRQ inputs must remain active until after the falling edge of the
first INTA#. If the IRQ input goes inactive before this time, a default IRQ7 occurs when the CPU acknowledges
the interrupt. This can be a useful safeguard for detecting interrupts caused by spurious noise glitches on the
IRQ inputs. To implement this feature, the IRQ7 routine is used for “clean up” simply executing a return
instruction, thus ignoring the interrupt. If IRQ7 is needed for other purposes, a default IRQ7 can still be detected
by reading the ISR. A normal IRQ7 interrupt sets the corresponding ISR bit; a default IRQ7 does not set this bit.
However, If a default IRQ7 routine occurs during a normal IRQ7 routine, the ISR remains set. In this case, it is
necessary to keep track of whether or not the IRQ7 routine was previously entered. If another IRQ7 occurs, it is
a default.
PRELIMINARY
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