82371AB Datasheet, PDF (182/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Counter I/O Port Read
The first method is to perform a simple read operation. To read the counter, which is selected with the A1, A0
inputs (port 040h, 041h, or 042h), the CLK input of the selected counter must be inhibited by using either the
GATE input or external logic. Otherwise, the count may be in the process of changing when it is read, giving an
undefined result. When reading the count value directly, follow the format programmed in the control register:
read LSB, read MSB, or read LSB then MSB. Within the PIIX4 timer unit, the GATE input on Counter 0 and
Counter 1 is tied high. Therefore, the direct register read should not be used on these two counters. The GATE
input of Counter 2 is controlled through I/O port 061h. If the GATE is disabled through this register, direct I/O
reads of port 042h will return the current count value.
Counter Latch Command
The Counter Latch Command latches the count at the time the command is received. This command is used to
ensure that the count read from the counter is accurate (particularly when reading a 2-byte count). The count
value is then read from each counter’s Count Register as was programmed by the Control Register.
The selected counter’s output latch (OL) latches the count at the time the Counter Latch Command is received.
This count is held in the latch until it is read by the CPU (or until the Counter is reprogrammed). The count is
then unlatched automatically and the OL returns to “following” the counting element (CE). This allows reading the
contents of the counters “on the fly” without affecting counting in progress. Multiple Counter Latch Commands
may be used to latch more than one counter. Each latched counter’s OL holds its count until it is read. Counter
Latch Commands do not affect the programmed mode of the counter in any way. The Counter Latch Command
can be used for each counter in the PIIX4 timer unit.
If a Counter is latched and then, some time later, latched again before the count is read, the second Counter
Latch Command is ignored. The count read will be the count at the time the first Counter Latch Command was
issued.
With either method, the count must be read according to the programmed format; specifically, if the counter is
programmed for 2-byte counts, 2 bytes must be read. The 2 bytes do not have to be read one right after the
other. Read, write, or programming operations for other counters may be inserted between them.
Another feature of the PIIX4 timer is that reads and writes of the same counter may be interleaved. For example,
if the Counter is programmed for 2-byte counts, the following sequence is valid:
• Read least significant byte.
• Write new least significant byte.
• Read most significant byte.
• Write new most significant byte.
If a counter is programmed to read/write 2-byte counts, a program must not transfer control between reading the
first and second byte to another routine which also reads from that same counter. Otherwise, an incorrect count
will be read.
Read Back Command
The third method uses the Read Back Command. The Read Back Command is used to determine the count
value, programmed mode, and current states of the OUT pin and Null Count flag of the selected counter or
counters. The Read Back Command is written to the Control Word Register, which causes the current states of
the above mentioned variables to be latched. The value of the counter and its status may then be read by I/O
access to the counter address.
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