82371AB Datasheet, PDF (72/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
4.2.1.7.
DBADDR—DMA Base and Current Address Registers (IO)
I/O Address:
Default Value:
Attribute:
DMA Channel 0—000h DMA Channel 4—0C0h
DMA Channel 1—002h DMA Channel 5—0C4h
DMA Channel 2—004h DMA Channel 6—0C8h
DMA Channel 3—006h DMA Channel 7—0CCh
Undefined (CPURST or Master Clear)
Read/Write
This Register works in conjunction with the Low Page Register. After an autoinitialization, this register retains the
original programmed value. Autoinitialize takes place after a TC. The address register is automatically
incremented or decremented after each transfer. This register is read/written in successive 8-bit bytes. The
programmer must issue the “Clear Byte Pointer Flip-Flop” command to reset the internal byte pointer and
correctly align the write prior to programming the Current Address Register. Autoinitialize takes place only after a
TC.
Bit
Description
15:0 Base and Current Address [15:0]. These bits represent address bits [15:0] used when forming the
24-bit address for DMA transfers.
4.2.1.8.
DBCNT—DMA Base and Current Count Registers (IO)
I/O Address:
Default Value:
Attribute:
DMA Channel 0—001h DMA Channel 4—0C2h
DMA Channel 1—003h DMA Channel 5—0C6h
DMA Channel 2—005h DMA Channel 6—0CAh
DMA Channel 3—007h DMA Channel 7—0CEh
Undefined (CPURST or Master Clear)
Read/Write
This register determines the number of transfers to be performed. The actual number of transfers is one more
than the number programmed in the Current Byte/Word Count Register when the value in the register is
decremented from zero to FFFFh, a TC is generated. Autoinitialize can only occur when a TC occurs. If it is not
autoinitialized, this register has a count of FFFFh after TC.
For transfers to/from an 8-bit I/O, the Byte/Word count indicates the number of bytes to be transferred. This
applies to DMA channels 0–3. For transfers to/from a 16-bit I/O, with shifted address, the Byte/Word count
indicates the number of 16-bit words to be transferred. This applies to DMA channels 5–7.
Bit
Description
15:0 Base and Current Byte/Word Count. These bits represent the 16-byte/word count bits used when
counting down a DMA transfer.
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