82371AB Datasheet, PDF (165/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

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82371AB (PIIX4)
ISA Bus refresh cycles are completely decoupled from DRAM Refresh. Transactions driven by PCI masters that
target ISA or IDE resources while refresh is active are held off with wait states until the refresh is complete.
ISA Master Initiated Refresh Cycle
If an ISA Bus master holds the ISA Bus longer than 15 µs, the ISA master must initiate memory refresh cycles. If
the ISA Bus master initiates a refresh cycle before it relinquishes the bus, it floats the address lines and control
signals and asserts the REFRESH# to PIIX4. PIIX4 drives address lines SA[7:0] and MEMR# onto the ISA Bus.
BALE is driven high and AEN is driven low for the entire refresh cycle.
If the ISA bus master holding the bus does not generate a Refresh request and PIIX4’s internal refresh request
is not serviced within the normal 15 microseconds, a refresh queue counter is incremented. The counter records
up to four incomplete refresh cycles, which are all executed as soon as PIIX4 gets the
ISA bus.
8.5. PCI DMA
PIIX4 supports two types of PCI DMA protocols: PC/PCI and distributed DMA. They are completely different
protocols that are used for different types of peripherals.
PC/PCI DMA uses dedicated REQUEST and GRANT signals to permit PCI devices to request transfers
associated with specific DMA channels. Upon receiving a request and getting control of the PCI bus, PIIX4
performs a two-cycle transfer. For example, if data is to be moved from the peripheral to main memory, PIIX4 will
first read data from the peripheral and then write it to main memory. The location in main memory is the Current
Address Registers in the 8237. PIIX4 supports up to three PC/PCI REQ/GNT pairs.
Distributed DMA is based on monitoring CPU accesses to the 8237. If the accesses are associated with DMA
channels that are “distributed” (in some PCI peripheral), then PIIX4 collects or distributes the data before letting
the CPU complete its accesses. This way the CPU thinks that it is accessing a standard 8237-based design,
even though the registers are not located in PIIX4.
A 16-bit register is included in the PIIX4 Function 0 configuration space at offset 90h. It is divided into seven 2-bit
fields that are used to configure the 7 DMA channels.
Each DMA channel can be configured to one of three options:
• Standard ISA (or EIO) DMA using the standard ISA DREQ/DACK signals.
• PC/PCI style DMA using the REQ/GNT signals.
• Distributed DMA.
It is not possible for a particular DMA channel to be configured for more than one style of DMA; however, the
seven channels can be programmed independently. For example, channel 3 could be set up for PC/PCI and
channel 5 set up for Distributed DMA.
Additional configuration is required separately for the PC/PCI and Distributed DMA functions and is described
below.
8.5.1. PC/PCI DMA
PIIX4 provides support for DMA across PCI using the PC/PCI DMA Protocol. The PCI DMA request/grant pairs,
REQ[A:C]# and GNT[A:C]#, can be configured for support of a PC/PCI DMA Expansion agent. The PCI DMA
Expansion agent can then provide DMA service or ISA Bus Master service using the PIIX4 DMA controller. The
REQ#/GNT# pair must follow the PC/PCI serial protocol described below.
PRELIMINARY
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