82371AB Datasheet, PDF (48/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
3.2.2. IO SPACE REGISTERS
Table 7. PCI Bus Master IDE I/O Registers
Offset From Mnemonic
Base Address
Register Name
00h
BMICP
Bus Master IDE Command (primary)
01h
—
Reserved
02h
BMISP
Bus Master IDE Status (primary)
03h
—
Reserved
04–07h
BMIDTPP
Bus Master IDE Descriptor Table Pointer (primary)
08h
BMICS
Bus Master IDE Command (secondary)
09h
—
Reserved
0Ah
BMISS
Bus Master IDE Status (secondary)
0Bh
—
Reserved
0C–0Fh
BMIDTPS
Bus Master IDE Descriptor Table Pointer (secondary)
NOTES:
1. The base address is programmable via the BMIBA Register (20−23h; function 1)
Access
R/W
—
R/W
—
R/W
R/W
—
R/W
—
R/W
3.3. Universal Serial Bus (USB) Configuration
The PIIX4 PCI function 2 contains a Universal Serial Bus Host and Root Hub with two connected USB ports.
This function supports the Universal Host Controller Interface (UHCI). The register set associated with USB
Host Controller is shown below with actual register descriptions given in the “USB Host Controller Register
Descriptions” section.
3.3.1. PCI CONFIGURATION REGISTERS (FUNCTION 2)
Table 8. PCI Configuration Registers—Function 2 (USB Interface)
Address Offset Mnemonic
Register Name
Access
00–01h
VID
Vendor Identification
RO
02–03h
DID
Device Identification
RO
04–05h
PCICMD
PCI Command
R/W
06–07h
PCISTS
PCI Device Status
R/W
08h
RID
Revision Identification
RO
09−0Bh
CLASSC
Class Code
RO
0Ch
—
Reserved
—
0Dh
MLT
Latency Timer
R/W
0Eh
HEDT
Header Type
RO
0F–1Fh
—
Reserved
—
20–23h
USBBA
USB IO Space Base Address
R/W
24–3Bh
—
Reserved
—
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