82371AB Datasheet, PDF (47/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
3.2. IDE Configuration
The PIIX4 PCI function 1 contains an IDE Controller capable of standard Programmed IO (PIO) transfers as well
as Bus Master transfer capability. This function also supports the “Ultra DMA/33” synchronous DMA mode of
data transfer. The register set associated with IDE Controller is shown below with the actual register descriptions
given in the “IDE Controller Register Descriptions” section.
3.2.1. PCI CONFIGURATION REGISTERS (FUNCTION 1)
Table 6. PCI Configuration Registers—Function 1 (IDE Interface)
Address Offset Mnemonic
Register Name
00–01h
VID
Vendor Identification
02–03h
DID
Device Identification
04–05h
PCICMD
PCI Command
06–07h
PCISTS
PCI Device Status
08h
RID
Revision Identification
09−0Bh
CLASSC
Class Code
0Ch
—
Reserved
0Dh
MLT
Master Latency Timer
0Eh
HEDT
Header Type
0F–1Fh
—
Reserved
20–23h
BMIBA
Bus Master Interface Base Address
24–3Fh
—
Reserved
40–43h
IDETIM
IDE Timing
44h
SIDETIM
Slave IDE Timing
45–47h
—
Reserved
48h
UDMACTL Ultra DMA/33 Control
49h
—
Reserved
4A–4Bh
UDMATIM Ultra DMA/33 Timing
4C–FFh
—
Reserved
Access
RO
RO
R/W
R/W
RO
RO
—
R/W
RO
—
R/W
—
R/W
R/W
—
R/W
—
R/W
—
PRELIMINARY
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INTEL CONFIDENTIAL
(until publication date)