82371AB Datasheet, PDF (243/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Table 43. On to POS Timings
Sym
Parameter
Min Max Unit Notes
t34 CPU_STP# and PCI_STP# Inactive to STPCLK# Active
1
RTC
1, 2
t35 STPCLK# Active to SLP# Active
1
RTC
1, 3
t36 SLP# Active to SUS_STAT[1:2]# Active
1
RTC
1
t37 SUS_STAT[1:2]# Active to CPU_STP# and PCI_STP# Active
1
RTC
1
t38 CPU_STP# and PCI_STP# Active to SUS[A]# Active
1
RTC
1
t39 CPU_STP# and PCI_STP# Active to Clocks Stopped
(if applicable)
2 PCICLK 4, 5
NOTES:
1. These signals are controlled off an internal RTC clock. 1 RTC unit is approximately 32 µs.
2. CPU_STP# and PCI_STP# will only be active if system is under clock control.
3. This transition will also wait for the Stop Grant cycle to execute.
4. It is up to the system vendor to determine if CPU_STP# and PCI_STP# signals are used to control system
clocks.
5. See Figure 18 and Figure 19 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
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