82371AB Datasheet, PDF (69/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
4.2.1.2.
DCM—DMA Channel Mode Register (IO)
I/O Address:
Default Value:
Attribute:
Channels 0–3—0Bh; Channels 4–7—0D6h
Bits[7:2]=0; Bits[1:0]=undefined (CPURST or Master Clear)
Write Only
Each channel has a 6-bit DMA Channel Mode Register. The Channel Mode Registers provide control over DMA
transfer type, transfer mode, address increment/decrement, and autoinitialization.
Bit
Description
7:6 DMA Transfer Mode. Each DMA channel can be programmed in one of four different modes:
Bits[7:6]
00
01
10
11
Transfer Mode
Demand mode
Single mode
Block mode
Cascade mode
5 Address Increment/Decrement Select. 0=Increment; 1=Decrement.
4 Autoinitialize Enable. 1=Enable; 0=Disable.
3:2 DMA Transfer Type. When Bits [7:6]=11, the transfer type bits are irrelevant.
Bits[3:2]
00
01
10
11
Transfer Type
Verify transfer
Write transfer
Read transfer
Illegal
1:0 DMA Channel Select. Bits [1:0] select the DMA Channel Mode Register written to by bits [7:2].
Bits[1:0]
00
01
10
11
Channel
Channel 0 (4)
Channel 1 (5)
Channel 2 (6)
Channel 3 (7)
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)