82371AB Datasheet, PDF (167/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
The three cases above require the following functionality in the PCI DMA expansion device:
1. Drive REQ# inactive for one clock to signal new request information.
2. Drive REQ# inactive for two clocks to signal that a request that had been granted the bus has gone inactive.
3. The REQ# and GNT# state machines must run independently and concurrently (i.e., a GNT# could be
received while in the middle of sending a serial REQ# or a GNT# could be active while REQ# is inactive).
PCI DMA Expansion Cycles
PIIX4’s support of the Mobile PC/PCI DMA Protocol currently consists of four types of cycles: Memory to I/O, I/O
to Memory, Verify, and ISA Master cycles. ISA Masters are supported through the use of a DMA channel that
has been programmed for cascade mode. Single Transfer Mode is implicitly supported as the case where the
DMA controller negates the DACK#/GNT# signal after one transfer has been completed or the DMA controller
toggles DACK# after every transfer. Single transfer mode does not require the requesting device to negate
DREQ# after a cycle has completed. Therefore, a PCI DMA agent that uses this mode must also sample the
GNT# signal and remove DACK# to the I/O DMA device when GNT# goes inactive.
The DMA controller does a two cycle transfer (a load followed by a store) as opposed to the ISA “fly-by” cycle for
PC/PCI DMA agents. The memory portion of the cycle generates a PCI memory read or memory write bus
cycle, its address representing the selected memory.
The I/O portion of the DMA cycle generates a PCI I/O cycle to one of four I/O addresses (Table 22). Note that
these cycles must be qualified by an active GNT# signal to the requesting device.
DMA Cycle Type
Normal
Normal TC
Verify
Verify TC
Table 22. DMA Cycle vs. I/O Address
DMA I/O Address
TC (A2)
00h
0
04h
1
0C0h
0
0C4h
1
PCI Cycle Type
I/O Read/Write
I/O Read/Write
I/O Read
I/O Read
For PCI DMA cycles, the I/O address indicates the type of DMA cycle taking place (whether its a normal or a
verify cycle, and if this is the last transfer of the buffer). Note that the A2 address line is encoded as the terminal
count signal for PCI cycles; A2 asserted during a PCI I/O cycle indicates the last transfer in the current DMA
buffer. To ensure that non Mobile PC/PCI compliant PCI I/O devices do not confuse Mobile PC/PCI DMA cycles
for normal I/O cycles, the addresses used by the PCI DMA cycles correspond to the slave addresses of the
Mobile PC/PCI DMA controller.
All PCI DMA I/O ports must be DWord aligned and can be either byte or word in size. This means that any PCI
DMA I/O port must always be connected to the lower data lines of the PCI data bus (Table 23).
The byte enables also reflect this during the I/O portion of a PCI DMA cycle. Table 24 illustrates the byte enable
state for any given PCI DMA cycle:
Table 23. PCI Data Bus vs. DMA I/O port size
PCI DMA I/O Port Size
PCI Data Bus Connection
Byte
AD[7:0]
PRELIMINARY
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