82371AB Datasheet, PDF (26/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
2.1.6. CPU INTERFACE SIGNALS
Name
A20M#
CPURST
FERR#
IGNNE#
INIT
INTR
26
Type
OD
OD
I
OD
OD
OD
Description
ADDRESS 20 MASK. PIIX4 asserts A20M# to the CPU based on combination of Port
92 Register, bit 1 (FAST_A20), and A20GATE input signal.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
CPU RESET. PIIX4 asserts CPURST to reset the CPU. PIIX4 asserts CPURST during
power-up and when a hard reset sequence is initiated through the RC register.
CPURST is driven inactive a minimum of 2 ms after PWROK is driven active. CPURST
is driven active for a minimum of 2 ms when initiated through the RC register. The
inactive edge of CPURST is driven synchronously to the rising edge of PCICLK. If a
hard reset is initiated through the RC register, PIIX4 resets its internal registers (in both
core and suspend wells) to their default state.
This signal is active high for Pentium processor and active-low for Pentium II processor
as determined by CONFIG1 signal.
For values During Reset, After Reset, and During POS, see the Suspend/Resume
and Resume Control Signaling section.
NUMERIC COPROCESSOR ERROR. This pin functions as a FERR# signal supporting
coprocessor errors. This signal is tied to the coprocessor error signal on the CPU. If
FERR# is asserted, PIIX4 generates an internal IRQ13 to its interrupt controller unit.
PIIX4 then asserts the INT output to the CPU. FERR# is also used to gate the IGNNE#
signal to ensure that IGNNE# is not asserted to the CPU unless FERR# is active.
IGNORE NUMERIC EXCEPTION. This signal is connected to the ignore numeric
exception pin on the CPU. IGNNE# is only used if the PIIX4 coprocessor error reporting
function is enabled. If FERR# is active, indicating a coprocessor error,
a write to the Coprocessor Error Register (F0h) causes the IGNNE# to be asserted.
IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the
Coprocessor Error Register is written, the IGNNE# signal is not asserted.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
INITIALIZATION. INIT is asserted in response to any one of the following conditions.
When the System Reset bit in the Reset Control Register is reset to 0 and the Reset
CPU bit toggles from 0 to 1, PIIX4 initiates a soft reset by asserting INIT. PIIX4 also
asserts INIT if a Shut Down Special cycle is decoded on the PCI Bus, if the RCIN#
signal is asserted, or if a write occurs to Port 92h, bit 0. When asserted, INIT remains
asserted for approximately 64 PCI clocks before being negated.
This signal is active high for Pentium processor and active-low for Pentium II processor
as determined by CONFIG1 signal.
Pentium Processor:
During Reset: Low
After Reset: Low
During POS: Low
Pentium II Processor:
During Reset: High
After Reset: High
During POS: High
CPU INTERRUPT. INTR is driven by PIIX4 to signal the CPU that an interrupt request
is pending and needs to be serviced. It is asynchronous with respect to SYSCLK or
PCICLK and is always an output. The interrupt controller must be programmed following
PCIRST# to ensure that INTR is at a known state.
During Reset: Low
After Reset: Low
During POS: Low
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)