82371AB Datasheet, PDF (261/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
I/O Location
0070h (bit 7 only)
Table 52. NMI Enable Bit Changes in Alternate Access Mode
R/W
Standard Mode Usage
ALT Access Mode
R Write Only for NMI Enable Bit
Read Bit Enable Bit
Table 53. Programmable Interval Timer Changes in Alternate Access Mode
I/O Location
R/W
Standard Mode Usage
ALT Access Mode
0040h
R Status Byte Counter 0
1st Read:
2nd Read:
3rd Read:
4th Read:
5th Read:
6th Read:
7th Read:
Status Byte Counter 0
CRL for Counter 0
CRM for Counter 0
CRL for Counter 1
CRM for Counter 1
CRL for Counter 2
CRM for Counter 2
0041h
R Status Byte Counter 1
Status Byte Counter 1
0042h
R Status Byte Counter 2
Status Byte Counter 2
The BIOS must perform seven consecutive reads from port 40h in alternate access mode. If BIOS deviates from
this it may get inaccurate data. It also allows BIOS to set the alt access bit and still read the status of all the
counters. Setting the Alt Access Mode automatically clears the high/low flip flop. When the ALT Access Mode is
entered the timers do not stop counting, hence the current values will change from the time the initial value is
read.
Table 54. Programmable Interrupt Controller
I/O Location
R/W
Standard Mode Usage
ALT Access Mode
0020h
R Interrupt Request Register for Cntrl 1 1st Read:
2nd Read:
3rd Read:
4th Read:
5th Read:
6th Read:
7th Read:
8th Read:
9th Read:
10th Read:
11th Read:
12th Read:
13th Read:
14th Read:
ICW1 for Cntrl 1
ICW2 for Cntrl 1
ICW3 for Cntrl 1
ICW4 for Cntrl 1
OCW1 for Cntrl 1
OCW2 for Cntrl 1
OCW3 for Cntrl 1
ICW1 for Cntrl 2
ICW2 for Cntrl 2
ICW3 for Cntrl 2
ICW4 for Cntrl 2
OCW1 for Cntrl 2
OCW2 for Cntrl 2
OCW3 for Cntrl 2
0021h
R In-Service Register for Cntrl 1
In-Service Register for Cntrl 1
00A0h
R Interrupt Request Register for Cntrl 2 Interrupt Request Register for Cntrl 2
00A1h
R In-Service Register for Cntrl 2
In-Service Register for Cntrl 2
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)