82371AB Datasheet, PDF (251/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Table 47. On to STR Timings
Sym
Parameter
Min Max Unit Notes
t67 CPU_STP# and PCI_STP# Inactive to STPCLK# Active
1
RTC
1, 2
t68 STPCLK# Active to SLP# Active
1
RTC
1, 3
t69 SLP# Active to SUS_STAT[1:2]# Active
1
RTC
1
t70 SUS_STAT[1:2]# Active to CPU_STP# and PCI_STP# Active
1
RTC
1
t71 CPU_STP# and PCI_STP# Active to Clocks Stopped
2 PCICLK 4, 5
t72 CPU_STP# and PCI_STP# Inactive to SUS[A:B]# Active
1
RTC
1
t73 SUS[A:B]# Active to PWROK Inactive
0
ns
6
t74 PWROK Inactive to CPU_STP# and PCI_STP# Float
1
RTC
1
t75 PWROK Inactive to PCI_RST# Active
1
RTC
1
t76 PWROK Inactive to CPURST Active
1
RTC
1
t77 PWROK Inactive to SLP# Inactive
1
RTC
1
t78 PWROK Inactive to STPCLK# Inactive
1
RTC
1
t79 CPU_STP# and PCI_STP# Float to Clocks Invalid
0
ns
7
t80 PWROK Inactive to Core Well Power Removed
0
ns
t81 Core Well Power Removed to PCI_STP# and CPU_STP# Invalid 0
ns
t82 Core Well Power Removed to PCIRST# Invalid
0
ns
t83 Core Well Power Removed to CPURST Invalid
0
ns
t84 Core Well Power Removed to SLP# Invalid
0
ns
t85 Core Well Power Removed to STPCLK# Invalid
0
ns
NOTES:
1. These signals are controlled off the internal RTC clock. 1 RTC is approximately 32 µs.
2. CPU_STP# and PCI_STP# will only be active if system is under clock control.
3. This transition will also wait for the Stop Grant cycle to execute.
4. It is up to the system vendor to determine if CPU_STP# and PCI_STP# signals are used to control system
clocks.
5. See Figure 18 and Figure 19 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.
6. It is up to the system vendor to determine if SUS[A:B]# signals are used to control system power planes. If
power remains applied to system board and PWROK stays active during STR, the PIIX4 signals remain in
the states shown after t73.
7. Clocks may or may not be running depending on condition of Power Supply voltages.
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
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