82371AB Datasheet, PDF (115/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
6.2.7. PORTSC—PORT STATUS AND CONTROL REGISTER (IO)
I/O Address:
Default:
Access:
Base + (10−11h)Port 0
Base + (12−13h)Port 1
0080h
Read/Write (WORD writeable only)
After a Power-up reset, Global reset, or Host Controller reset, the initial conditions of a port are: No device
connected, Port disabled, and the bus line status is 00 (single-ended zero). Note: If a device is attached, the port
state will transition to the attached state and system software will process this as with any status change
notification. It make take up to 64 USB bit times for the port transition to occur. If the Host Controller is in global
suspend mode, then, if any of bits [6,3,1] gets set, the Host Controller will signal a global resume. Refer to
Chapter 11 of the USB Specification for details on hub operation.
Bit
Description
15:13 Reserved. Must be written as 0s when writing this register.
12 Suspend—R/W. 1=Port in suspend state. 0=Port not in suspend state. This bit should not be written
to a 1 if global suspend is active (bit 3=1 in the USBCMD register). Bit 2 and bit 12 of this register
define the hub states as follows:
Bits [12,2]
x0
01
11
Hub Port State
Disable
Enable
Suspend
When in suspend state, downstream propagation of data is blocked on this port, except for single-
ended 0 resets (global reset and port reset). The blocking occurs at the end of the current
transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the
port is sensitive to resume detection. Note that the bit status does not change until the port is
suspended and that there may be a delay in suspending a port if there is a transaction currently in
progress on the USB.
11 Over-current Indicator Change—R/WC. 1=A change from 1 to 0 has been detected on the Over-
current (OC[X]#) pin for this port. 0=No change has been detected. Software sets this bit to 0 by
writing a 1 to it.
10 Over-current Indicator—RO. 1=Overcurrent pin (OC[X]#) for this port is at logic 0 indicating over-
current condition. 0=Overcurrent pin for this port is at logic 1 indicating a normal condition.
If asserted, the corresponding port is disabled.
9 Port Reset—R/W. 1=Port is in Reset. 0=Port is not in Reset. When in the Reset State, the port is
disabled and sends the USB Reset signaling. Note that host software must guarantee that the
RESET signaling is active for the proper amount of time as specified in the USB Specification.
8 Low Speed Device Attached—RO. 1=Low speed device is attached to this port. 0=Full speed
device. Writes have no effect.
7 Reserved—RO. Always read as 1.
6 Resume Detect—R/W. 1=Resume detected/driven on port. 0=No resume (K-state) detected/driven
on port. Software sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit to a 1
if a J-to-K transition is detected while the port is in the Suspend state. Note that when this bit is 1, a
K-state is driven on the port as long as this bit remains 1 and the port is still in suspend state. Writing
a 0 (from 1) causes the port to send a low speed EOP. This bit will remain a 1 until the EOP has
completed.
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)