82371AB Datasheet, PDF (137/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
7.2. Power Management IO Space Registers
The “Base” address is programmed in the PIIX4 PCI Configuration Space for Function 3, Offset 40h–43h.
7.2.1. PMSTS—POWER MANAGEMENT STATUS REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (00h)
00h
Read/Write
Bit
Description
15 Resume Status (RSM_STS)—R/WC. 1=An enabled resume event has occurred. 0=An enabled
resume event has not occurred. PIIX4 sets this bit to 1 upon detection of the resume event and then
transitions the system to the on state. This bit can only be set by hardware and can only be cleared
by writing a 1 to this bit position.
14:12
11
Reserved.
Power Button Override Status (PWRBTNOR_STS)—R/WC. 1=Power Button Override has been
signaled. 0=Power Button Override has not been signaled. This bit is set when Power Button
Override has been enabled and the PWRBTN# signal has been continuously asserted for greater
than 4 seconds. PIIX4 automatically transitions the system into the soft off state and clears the
PWRBTN_STS bit. This bit is only set by hardware and can only be reset by writing a 1 to this bit
position.
10 RTC Status (RTC_STS)—R/WC. 1=RTC alarm has been signaled. 0=RTC alarm has not been
signaled. This bit is set when the internal RTC asserts its IRQ8 signal. This bit is only set by
hardware and can only be reset by writing a 1 to this bit position.
9 Reserved.
8 Power Button Status (PWRBTN_STS)—R/WC. 1=PWRBTN# signal has been asserted.
0=PWRBTN# signal has not been asserted. There is a 16 ms delay from external signal assertion to
the setting of this bit due to internal switch debounce circuitry. This bit is only set by hardware and
can only be reset by writing a 1 to this bit position. If the PWRBTN# signal is held LOW for more than
4 seconds, then this bit is cleared and the PWRBTNOR_STS bit is set.
7:6 Reserved.
5 Global Status (GBL_STS)—R/WC. 1=SCI has been generated due a write of 1 to the BIOS_RLS
bit. 0=No SCI has been generated due to write to BIOS_RLS bit. The GLB_EN bit must be set to
enable the SCI generation. This bit is only set by hardware and can only be reset by writing a 1 to
this bit position.
4 Bus Master Status (BM_STS)—R/WC. 1=PCIREQ[0:3] or PHOLD# has been asserted (PCI Bus
Master request). 0=No Bus Master request. This bit is set when PCIREQ[0:3] or PHOLD# is
asserted and can only be cleared by writing a 1 to this bit position.
3:1 Reserved.
0 Timer Overflow Status (TMROF_STS)—R/WC. 1=Bit 23 of the 24-bit Power Management timer
has toggled. 0=Bit has not toggled. When the TMROF_EN is set then the setting of the TMROF_STS
bit will additionally generate an SCI. This bit is only set by hardware and can only be reset by writing
a 1 to this bit position.
PRELIMINARY
137
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)