82371AB Datasheet, PDF (68/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Bit
Description
2 Upper RAM Enable. 0=Accesses to RTC Upper 128-byte extended bank at I/O address 72–73h is
disabled. Accesses will be forwarded to ISA bus as determined by bit 5 of this register (default).
1=Accesses to 72–73h are forwarded to RTC Upper 128-byte extended bank.
1 Reserved.
0 RTC Enable. 0=Accesses to RTC Lower 128-byte standard bank at I/O address 70–71h is disabled.
Accesses will be forwarded to ISA bus as determined by bit 5 of this register. 1=Accesses to 70–71h
are forwarded to RTC Lower 128-byte standard bank.
When this bit is reset, the upper bank of RAM may still be accessed (enabled via bit 2 in this
register).
4.2. PCI to ISA/EIO Bridge IO Space Registers (IO)
4.2.1. DMA REGISTERS
PIIX4 contains DMA circuitry that incorporates the functionality of two 82C37 DMA controllers (DMA1 and
DMA2). The DMA registers control the operation of the DMA controllers and are all accessible from the Host
CPU via the PCI Bus interface. In addition, some of the registers are accessed from the ISA Bus via ISA I/O
space. Unless otherwise stated, a CPURST sets each register to its default value.
4.2.1.1.
DCOM—DMA Command Register (IO)
I/O Address:
Default Value:
Attribute:
Channels 0–3—08h; Channels 4–7—0D0h
00h (CPURST or Master Clear)
Write Only
This 8-bit register controls the configuration of the DMA. Note that disabling channels 4–7 also disables channels
0–3, since channels 0–3 are cascaded onto channel 4.
Bit
Description
7 DACK# ACTIVE Level (DACK#[3:0, (7:5)]). 1=Active high; 0=Active low.
6 DREQ Sense Assert Level (DREQ[3:0, (7:5)]). 1=Active Low; 0=Active high.
5 Reserved. Must be 0.
4 DMA Group Arbitration Priority. 1=Rotating priority; 0=Fixed priority.
3 Reserved. Must be 0.
2 DMA Channel Group Enable. 1=Disable; 0=Enable.
1:0 Reserved. Must be 0.
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