82371AB Datasheet, PDF (185/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
8.9.1.1.
Control Register A
Address Offset:
Default Value:
Attribute:
0Ah
NA (This register is not affected by any system reset signal.)
Read/Write
This register is used for general configuration of the RTC functions.
Bits
Description
7 Update in Progress (UIP). This bit may be monitored as a status flag. 1=Signifies that the update of
the timing registers is soon to occur or is in progress.
0=Signifies that the update cycle will not start for at least 244 µs. The time, calendar, and alarm
information in RAM is always available when the UIP bit is 0.
6:4 Division Chain Select (DVx). These three bits control the divider chain for the oscillator.
DV2
DV1
DV0 Function
0
1
0
Normal Operation
1
1
X
Divider Reset
1
0
1
Bypass 15 stages (test mode only)
1
0
0
Bypass 10 stages (test mode only)
0
1
1
Bypass 5 stages (test mode only)
0
1
1
Invalid
0
0
0
Invalid
3:0 Rate Select Bits (RSx). Selects one of 13 taps of the 15 stage divider chain. The selected tap can
generate a periodic interrupt if the PIE bit is set in register B. Otherwise, this tap sets the PF flag of
register C. If the periodic interrupt is not to be used, these bits should all be set to 0.
Bits[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
Periodic Rate
none
3.90625 ms
7.8125 ms
122.070 µs
244.141 µs
488.281 µs
976.5625 µs
1.953125 ms
Bits[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
Periodic Rate
3.90625 ms
7.8125 ms
15.625 ms
31.25 ms
62.5 ms
125 ms
250 ms
500 ms
PRELIMINARY
185
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)