82371AB Datasheet, PDF (201/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

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82371AB (PIIX4)
11.0. POWER MANAGEMENT FUNCTIONAL DESCRIPTION
11.1. Power Management Overview
The PIIX4 power management function provides a wide range of capabilities and configuration options allowing a
system designer to implement a wide range of power saving modes.
PIIX4 provides for four main areas of power management:
• Clock Control and Processor Complex Management
• Peripheral Device Management
• System Management (SMI Generation, System Management Bus)
• System Suspend and Resume
PIIX4 uses several mechanisms to help the power management software initiate and manage the transitions
between the power managed states. These include system-wide and peripheral event monitors to identify idle
and wake-up conditions, Intel’s System Management Interrupt (SMI#) support, Advanced Power Management
(APM) 1.2 interface, Pentium and Pentium II processor STPCLK# and SLP# Clock Control, Suspend/Resume
Hardware, and System Management Bus. PIIX4 supports the Advanced Configuration and Power Interface
(ACPI) specification.
System power management functions under a combination of both hardware and software control. The software
consists of System Management Mode (SMM) BIOS for legacy control and Operating System (OS) for ACPI.
The basic operation consists of software setting up the desired configuration and power management mode and
corresponding power savings level. The hardware then performs the necessary actions to maintain the power
mode. PIIX4 also monitors the system for events which may require changing the system power mode. When
one of these events is detected, PIIX4 informs the software, which makes the decision to change power modes.
This is done by a System Management Interrupt (SMI#) for legacy SMM BIOS or a System Control Interrupt
(SCI) for ACPI OS.
Brief descriptions of primary power management functions follow. More complete descriptions are provided later
in this section.
Clock Control: When the operating system, application program, or system software is not performing useful
work, the processor complex (Processor, Host Bridge, DRAM, L2 Cache) does not need to be executing cycles
and, therefore, can be placed in a Standby mode.
• Flexible STPCLK# Mechanism for Host Clock Control
• Throttling: STPCLK# Duty Cycle Control for Low Frequency Emulation
• Stop Grant State: With Processor Clock input RUNNING
• Stop Clock State: With Processor Clock input STOPPED
• Clock Wake-up (Clock Break Events) from Interrupts, Device Monitors, Bus Activity.
• Burst Mechanism for Hardware-Controlled Return to Standby
• Fast and Slow Burst timers
• PCI Clock Control (CLKRUN#) is independent from Host Clock Control.
• SRAM ZZ mode for L2 power management during Standby.
• Thermal Management Input for Clock Throttling during critical thermal condition.
Peripheral Device Management: Peripheral device resources are monitored to detect when a specific
device is idle. PIIX4 then informs system power management software, which can place that individual device
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
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