82371AB Datasheet, PDF (61/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
4.1.13. MSTAT—MISCELLANEOUS STATUS REGISTER (FUNCTION 0)
Address Offset:
Default Value:
Attribute:
6A–6Bh
0000h
Read/Write
This register provides miscellaneous status and control functions.
Bit
Description
15 SERR# Generation Due To Delayed Transaction Time-out—R/WC. PIIX4 sets this bit to a 1
when it generates SERR# due to a delayed transaction time-out caused by expiration of the PCI
delayed transaction discard timer. Software sets this bit to a 0 by writing a 1 to it.
14:8 Reserved.
7 Host-to-PCI Bridge Retry Enable—R/W. 1=Enable. 0=Disable. This bit, when enabled, causes
PIIX4 to retry, without initiating a delayed transaction, CPU initiated, non-LOCK#, PCI cycles.
No delayed transactions to PIIX4 may currently be pending and passive release must be active.
Delayed Transactions and Passive Release must both be enabled via the DLC register (function 0,
offset 82h). When disabled, PIIX4 accepts these cycles as normal, which may include retry with
initiation of a delayed transaction.
6:0 Reserved.
4.1.14. MBDMA[1:0]—MOTHERBOARD DEVICE DMA CONTROL REGISTERS (FUNCTION 0)
Address Offset :
Default Value:
Attribute:
76h—MBDMA0#; 77h—MBDMA1#
04h
R/W
These registers enable and disable a type F DMA transfer (3 SYSCLK) for a particular DMA channel.
Bit
Description
7 Type F and DMA Buffer Enable (FAST). 1=Enable for the channel selected by bits[2:0]. 0=Disable
for the channel selected by bits[2:0].
6:4 Reserved.
3 Reserved. Read as 1.
2:0 Type F DMA Channel Routing (CHNL). When FAST=1, this field enables type F transfers and the
4-byte DMA buffer for an ISA peripheral on the selected channel.
Bits[2:0]
000
001
010
011
DMA channel
0
1
2
3
Bits[2:0]
100
101
110
111
DMA channel
default (disabled)
5
6
7
PRELIMINARY
61
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)