82371AB Datasheet, PDF (27/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Name
NMI
SLP#
SMI#
STPCLK#
Type
OD
OD
OD
OD
Description
NON-MASKABLE INTERRUPT. NMI is used to force a nonmaskable interrupt to the
CPU. PIIX4 generates an NMI when either SERR# or IOCHK# is asserted, depending
on how the NMI Status and Control Register is programmed. The CPU detects an NMI
when it detects a rising edge on NMI. After the NMI interrupt routine processes the
interrupt, the NMI status bits in the NMI Status and Control Register are cleared by
software. The NMI interrupt routine must read this register to determine the source of
the interrupt. The NMI is reset by setting the corresponding NMI source enable/disable
bit in the NMI Status and Control Register. To enable NMI interrupts, the two NMI
enable/disable bits in the register must be set to 0, and the NMI mask bit in the NMI
Enable/Disable and Real Time Clock Address Register must be set to 0. Upon
PCIRST#, this signal is driven low.
During Reset: Low
After Reset: Low
During POS: Low
SLEEP. This signal is output to the Pentium II processor in order to put it into Sleep
state. For Pentium processor it is a No Connect.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
SYSTEM MANAGEMENT INTERRUPT. SMI# is an active low synchronous output that
is asserted by PIIX4 in response to one of many enabled hardware or software events.
The CPU recognizes the falling edge of SMI# as the highest priority interrupt in the
system, with the exception of INIT, CPURST, and FLUSH.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
STOP CLOCK. STPCLK# is an active low synchronous output that is asserted by PIIX4
in response to one of many hardware or software events. STPCLK# connects directly to
the CPU and is synchronous to PCICLK.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)