82371AB Datasheet, PDF (187/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
8.9.1.3.
Control Register C
Address Offset:
Default Value:
Attribute:
0Ch
00h
Read/Write
This register is used for various flags. All flag bits are cleared upon active RSMRST# or a read of Register C.
Bits
Description
7 Interrupt Request Flag (IRQF). Interrupt Request Flag=PF * PIE + AF * AIE + UF *UFE. This also
causes the CH_IRQ_B signal to be asserted.
6 Periodic Interrupt Flag (PF). Periodic interrupt Flag is 1 when the tap as specified by the RS bits of
register A is 1. If no taps are specified, this flag bit will remain at 0.
5 Alarm Flag (AF). 1=All Alarm values match the current time.
4 Update-ended Flag (UF). UF=1 immediately following an update cycle for each second.
3:0 Reserved. Read as 0.
8.9.1.4.
Control Register D
Address Offset:
Default Value:
Attribute:
0Dh
NA (This register is not affected by any system reset signal.)
Read/Write
This register is used for various flags.
Bits
Description
7 Valid RAM and Time Bit (VRT). This bit is set to 1 when the PWRGD signal is asserted. This feature
is not typically used. This bit should always be set to 0 during a write to this register.
6 Reserved. This bit always returns a 0 and should be set to 0 during register writes.
5:0 Date Alarm (DA). These bits store the date of month alarm value. If set to 000000, a ‘don’t care’ state
is assumed. The host must configure the date alarm for these bits to operate, even though the bits can
be written at any time. If the date alarm is not enabled, these bits will return zeros to mimic the
functionality of the Motorola* 146818B. These bits are not affected by RSMRST#.
PRELIMINARY
187
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)