82371AB Datasheet, PDF (79/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
4.2.2.9.
ELCR1—Edge/Level Control Register (IO)
I/O Address:
Default Value:
Attribute:
INT CNTRL-1—4D0h
00h
Read/Write
ELCR1 register allows IRQ[3:7] to be edge or level programmable on an interrupt by interrupt basis. IRQ0, IRQ1
and IRQ2 are not programmable and are always edge sensitive. When level triggered, the interrupt is signaled
active when input IRQ signal is high.
Bit
Description
7 IRQ7 ECL. 0=Edge Triggered mode; 1=Level Triggered mode.
6 IRQ6 ECL. 0=Edge Triggered mode; 1=Level Triggered mode.
5 IRQ5 ECL. 0=Edge Triggered mode; 1=Level Triggered mode.
4 IRQ4 ECL. 0=Edge Triggered mode; 1=Level Triggered mode.
3 IRQ3 ECL. 0=Edge Triggered mode; 1=Level Triggered mode.
2:0 Reserved. Must be 0.
4.2.2.10.
ELCR2—Edge/Level Control Register (IO)
I/O Address:
Default Value:
Attribute:
INT CNTRL-2—4D1h
00h
Read/Write
ELCR2 register allows IRQ[15,14,12:9] to be edge or level programmable on an interrupt by interrupt basis. Note
that, IRQ[13,8#] are not programmable and are always edge sensitive. When level triggered, the interrupt is
signaled active when input IRQ signal is high.
Bit
Description
7 IRQ15 ECL. 0=Edge Triggered mode; 1=Level Triggered mode.
6 IRQ14 ECL. 0=Edge Triggered mode; 1=Level Triggered mode.
5 Reserved. Must be 0.
4 IRQ12 ECL. 0=Edge Triggered mode; 1=Level Triggered mode.
3 IRQ11 ECL. 0=Edge Triggered mode; 1=Level Triggered mode.
2 IRQ10 ECL. 0=Edge Triggered mode; 1=Level Triggered mode.
1 IRQ9 ECL. 0=Edge Triggered mode; 1=Level Triggered mode.
0 Reserved. Must be 0.
PRELIMINARY
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