82371AB Datasheet, PDF (209/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
• PIIX4 waits up to 2–32-kHz clock periods after receiving the Stop Grant Bus Cycle to allow the Host Bridge
to complete pending cycles to DRAM. PIIX4 then asserts the SUSTAT1# signal to the Host
Bridge {1}.
• PIIX4 waits an additional 32-khz clock period while the Host Bridge switches from Normal Refresh to
Suspend Refresh, then asserts the CPU_STP# signal to the clock synthesizer which stops the Host clock to
the processor, host bridge, L2 SRAM, and SDRAM. The processor is now in the Stop Clock State {3}.
• The processor will stay in this state until a Stop Break or Burst Event occurs.
Leaving the processor Stop Clock State:
• A Stop Break or Burst Event occurs.
• PIIX4 negates the CPU_STP# signal to the clock synthesizer to start the Host clocks.
• PIIX4 waits for the processor PLL to start and lock (about 1 ms + 1 32-khz period) then negates the
SUS_STAT1# signal {4}. The Host Bridge will switch from Suspend Refresh to Normal Refresh after the
SUS_STAT1# signal is negated.
• PIIX4 waits up to 2–32-kHz periods and then negates the STPCLK# signal {5}. If the ZZ signal was enabled,
PIIX4 will negate the ZZ signal a minimum of 2 PCI clocks before the STPCLK# signal is negated {8}.
• Processor returns to the On state and resumes normal execution.
• Software re-enables the Host Bridge PCI Arbiter.
NOTE
PCI masters must not be granted the bus before the processor is ready to snoop the PCI cycles
(STPCLK# negated). Therefore, when the system enters the Stop Clock State the PCI Arbiter (Host
Bridge) must be disabled. When the PCI arbiter is disabled any request to the arbiter (REQ# or PHOLD#
from PIIX4) should generate an SMI# so that power management software can re-enable the arbiter.
These requests can be trapped using the Device 8 (LPT) Peripheral Device Monitor.
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)