82371AB Datasheet, PDF (169/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

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82371AB (PIIX4)
Read/Write Cycles Protocol
For read cycles on the PCI bus that correspond to distributed DMA channels, PIIX4 performs the following:
• PIIX4 issues a PCI retry to terminate this cycle.
• PIIX4 requests the PCI bus. Upon being granted access to the bus, PIIX4 performs one or more read cycles
to the 8237 and/or the peripherals. The I/O location of the read cycle is calculated based on several
parameters: the DDMA Base Pointer registers in the PCI Configuration space, the DMA channel number (0–
3, 5–7), and the register location (0h–Fh).
• PIIX4 uses the data obtained via the read cycles (along with the value in the 8237) to construct the proper
data value.
• When the CPU retries the cycle, PIIX4 responds with the proper data value.
The specific number of read cycles and merging format for each of the 8237 registers is covered in Table 25.
For write cycles on the PCI bus that correspond to distributed DMA channels, PIIX4 performs the following:
• PIIX4 issues a PCI retry to terminate this cycle.
• PIIX4 requests the PCI bus. Upon being granted access to the bus, PIIX4 performs one or more write cycles
to the 8237 and/or the peripherals. The I/O location of the write cycle is calculated based on several
parameters: the DDMA Base Pointer registers in the PCI Configuration space, the DMA channel number (0–
3, 5–7), and the register location (0h–Fh).
• PIIX4 uses the data obtained via the CPU’s original write cycles to determine the proper values to write to
the peripherals and to the 8237.
• When the CPU retries the cycle, PIIX4 lets it complete normally.
Calculating the I/O Address
When PIIX4 attempts to access the PCI peripheral, it performs I/O read or write cycles. The exact address to
use is calculated as follows:
Bits [31:16] are 0.
Bits [15:6] are indicated by the Base Pointer in the PCI Configuration Space for Function 0. The base pointer at
offset 92h is used for DMA channels 0–3. The base pointer at offset 94h is used for DMA channels 5–7.
Bits [5:4] are determined by the DMA channel number being accessed.
DMA Channel
Number
0
1 or 5
2 or 6
3 or 7
Bits [5:4]
00
01
10
11
Bits [3:0] are determined by the register being accessed.
NOTE
The mapping in the peripheral is Not the same as in the 8237. Table 25 shows the mapping of the 8237
register to the Distributed DMA peripheral.
PRELIMINARY
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