82371AB Datasheet, PDF (25/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Name
IRQ 3:7, 9:11,
14:15
IRQ8#/
GPI6
IRQ9OUT#/
GPO29
IRQ 12/M
PIRQ[A:D]#
SERIRQ/
GPI7
Type
I
I/O
O
I
I/OD
PCI
I/O
Description
INTERRUPT REQUESTS 3:7, 9:11, 14:15. The IRQ signals provide both system
board components and ISA Bus I/O devices with a mechanism for asynchronously
interrupting the CPU. These interrupts may be programmed for either an edge
sensitive or a high level sensitive assertion mode. Edge sensitive is the default
configuration.
An active IRQ input must remain asserted until after the interrupt is acknowledged. If
the input goes inactive before this time, a default IRQ7 is reported in response to the
interrupt acknowledge cycle.
IRQ 8#. IRQ8# is always an active low edge triggered interrupt and can not be
modified by software.
IRQ8# must remain asserted until after the interrupt is acknowledged. If the input
goes inactive before this time, a default IRQ7 is reported in response to the interrupt
acknowledge cycle.
If using the internal RTC, then this can be programmed as a general-purpose input. If
enabling an APIC, this signal becomes an output and must not be programmed as a
general purpose input.
IRQ9OUT#. IRQ9OUT# is used to route the internally generated SCI and SMBus
interrupts out of the PIIX4 for connection to an external IO APIC. If APIC is disabled,
this signal pin is a General Purpose Output.
During Reset: High
After Reset: High During POS: IRQ9OUT#/GPO
INTERRUPT REQUEST 12. In addition to providing the standard interrupt function
as described in the pin description for IRQ[3:7,9:11,14:15], this pin can also be
programmed to provide the mouse interrupt function.
When the mouse interrupt function is selected, a low to high transition on this signal
is latched by PIIX4 and an INTR is generated to the CPU as IRQ12. An internal
IRQ12 interrupt continues to be generated until a Reset or an I/O read access to
address 60h (falling edge of IOR#) is detected.
PROGRAMMABLE INTERRUPT REQUEST. The PIRQx# signals are active low,
level sensitive, shareable interrupt inputs. They can be individually steered to ISA
interrupts IRQ [3:7,9:12,14:15]. The USB controller uses PIRQD# as its output
signal.
SERIAL INTERRUPT REQUEST. Serial interrupt input decoder, typically used in
conjunction with the Distributed DMA protocol.
If not using serial interrupts, this pin can be used as a general-purpose input.
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)