82371AB Datasheet, PDF (245/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Table 44. POS to On (w/Processor & PCI Reset) Timings
Sym
Parameter
Min Max Unit Notes
t40 Resume Event to SUS[A]# Inactive
1
RTC
1
t41 Resume Event to PCI_RST# Active
1
RTC
1
t42 Resume Event to CPURST Active
1
RTC
1
t43 Resume Event to SLP# Inactive
1
RTC
1
t44 Resume Event to STPCLK# Inactive
1
RTC
1
t45 SUS[A]# Inactive to PCI_STP# and CPU_STP# Inactive
16
ms
2
t46 PCI_STP# and CPU_STP# Inactive to Clocks Running
2 PCICLK 3
t47 PCI_STP# and CPU_STP# Inactive to SUS_STAT[1:2]# Inactive
1
ms
t48 SUS_STAT[1:2]# Inactive to PCI_RST# Inactive
1
RTC
1
t49 PCI_RST# Inactive to PCI_STP#; CPU_STP# allowed to change
1
RTC
1
t50 PCI_RST# Inactive to CPURST Inactive
1
RTC
1
NOTES:
1. These signals are controlled off an internal RTC clock. 1 RTC unit is approximately 32 µs.
2. This transition requires both a minimum of 16-ms wait for clock synthesizer PLL lock and PWROK to be
active. If PWROK goes active after 16 ms from SUS[A:C]# inactive, the transition will occur a minimum of 1
RTC period from PWROK active. PWROK remains active throughout standard POS system usage.
3. See Figure 18 and Figure 19 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.
PRELIMINARY
245
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)