82371AB Datasheet, PDF (134/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
7.1.25. DEVRESJ—DEVICE RESOURCE J (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
7C–7Fh
00h
Read/Write
Bit
Description
31:21 Reserved.
20 Generic I/O Decode 1 Enable (IO_EN_GDEC1)—R/W. 1=Enable accesses to the I/O address
range selected by the IO_MASK_GDEC1 and IO_BASE_GDEC1 fields to be claimed by PIIX4 and
forwarded to the ISA/EIO bus. 0=Disable.
19:16
Generic Decode 1 I/O Mask (IO_MASK_GDEC1)—R/W. This field specifies the 4-bit I/O base
address mask used to determine the IO address range size. IO_MASK_GDEC1(bits[19:16])
correspond to AD[3:0]. A ‘1’ in a bit position indicates that the corresponding address bit is masked
(i.e., ignored) when performing the decode. Note that programming these bits to certain patterns
(such as 1001) results in a split address range.
15:0 Generic Decode 1 I/O Base Address (IO_BASE_GDEC1)—R/W. This field specifies the 16-bit I/O
base address range (AD[15:0]) for the generic decode range 1. When this field is combined with
IO_MASK_GDEC1 field, an I/O range is defined starting from the base address register value to the
size defined by the mask register.
7.1.26. PMREGMISC—MISCELLANEOUS POWER MANAGEMENT (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
80h
00h
Read/Write
This register contains miscellaneous functionality associated with the PIIX4 Power Management capabilities.
Bit
Description
7:1 Reserved.
0 Power Management IO Space Enable (PMIOSE)—R/W. 1=Enable. 0=Disable. This bit controls the
access to the Power Management I/O space registers whose base address is described in the
Power Management Base Address register. If this bit is set, access to the power management IO
registers are enabled. The base address register for the I/O registers must be programmed before
this bit is set. When disabled, all IO accesses associated with Power Management Base Address
are disabled. This bit functions independent of the state of Function 3 IO Space Enable (IOSE) bit
(PCICMD register, bit 0).
134
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)