82371AB Datasheet, PDF (59/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
4.1.10. PIRQRC[A:D]—PIRQX ROUTE CONTROL REGISTERS (FUNCTION 0)
Address Offset :
Default Value:
Attribute:
60h (PIRQRCA#)–63h (PIRQRCD#)
80h
R/W
These registers control the routing of the PIRQ[A:D]# signals to the IRQ inputs of the interrupt controller. Each
PIRQx# can be independently routed to any one of 11 interrupts. All four PIRQx# lines can be routed to the
same IRQx input. Note that the IRQ that is selected through bits [3:0] must be set to level sensitive mode in the
corresponding ELCR Register. When a PIRQ signal is routed to an interrupt controller IRQ, PIIX4 masks the
corresponding IRQ signal.
Bit
Description
7 Interrupt Routing Enable. 0=Enable; 1=Disable.
6:4 Reserved. Read as 0s.
3:0 Interrupt Routing. When bit 7=0, this field selects the routing of the PIRQx to one of the interrupt
controller interrupt inputs.
Bits[3:0]
0000
0001
0010
0011
0100
0101
IRQ Routing
Reserved
Reserved
Reserved
IRQ3
IRQ4
IRQ5
Bits[3:0]
0110
0111
1000
1001
1010
IRQ Routing
IRQ6
IRQ7
Reserved
IRQ9
IRQ10
Bits[3:0]
1011
1100
1101
1110
1111
IRQ Routing
IRQ11
IRQ12
Reserved
IRQ14
IRQ15
4.1.11. SERIRQC—SERIAL IRQ CONTROL REGISTER (FUNCTION 0)
Address Offset :
Default Value:
Attribute:
64h
10h
R/W
This register controls the Start Frame Pulse Width generated on the Serial Interrupt signal (SERIRQ).
Bit
Description
7 Serial IRQ Enable. 1=Enable (bit 16 in register offset B0h–B3h must also be 1). 0=Disable.
6 Serial IRQ Mode Select. 1=Serial Interrupts operate in Continuous mode. 0=Serial Interrupts
operate in Quiet mode.
5:2 Serial IRQ Frame Size. These bits select the frame size used by the Serial IRQ logic. The default is
0100b indicating a frame size of 21 (17+4). These bits are readable and writeable, however the only
programmed value supported by PIIX4 is 0100b. All other frame sizes are unsupported.
1:0 Start Frame Pulse Width. These bits define the Start Frame pulse width generated by the Serial
Interrupt control logic.
Bits[1:0]
00
01
10
11
Pulse Width (PCI Clocks)
4 Clocks
6 Clocks
8 Clocks
Reserved
PRELIMINARY
59
4/9/97 2:23 PM PIIX4aDS
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(until publication date)