82371AB Datasheet, PDF (157/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

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82371AB (PIIX4)
8.2. PCI Interface
PIIX4 incorporates a fully PCI Bus compatible master and slave interface. As a PCI master, PIIX4 runs cycles on
behalf of DMA, ISA masters, bus master IDE, or USB. As a PCI slave, PIIX4 accepts cycles initiated by PCI
masters targeted for PIIX4’s internal register set or the ISA bus. PIIX4 directly supports the PCI interface running
at either 30 or 33 MHz.
8.2.1. TRANSACTION TERMINATION
PIIX4 supports the standard PCI cycle terminations as described in the PCI Local Bus specification.
PIIX4 as Master—Master-Initiated Termination: PIIX4 supports three forms of master-initiated termination: 1.)
Normal termination of a completed transaction, 2.) Normal termination of an incomplete transaction due to time-
out (applies to line buffer operations-IDE Bus Master, 3.) Abnormal termination due to the slave not responding
to the transaction (Abort).
PIIX4 as a Master—Response to Target-Initiated Termination: As a master, PIIX4 responds correctly to the
standard target-terminations—Target-Abort, Retry, or Disconnect.
PIIX4 as a Target—Target-Initiated Termination: PIIX4 supports three forms of Target-initiated Termination—
Disconnect, Retry, Target Abort.
8.2.2. PARITY SUPPORT
As a master, PIIX4 generates address parity for read/write cycles and data parity when PIIX4 is providing the
data. As a slave, PIIX4 generates data parity for read cycles. PIIX4 does not check parity and does not generate
SERR# due to an address parity error. However, PIIX4 does generate an NMI when another PCI device asserts
SERR# (if enabled).
PAR is the calculated parity signal. PAR is even parity and is calculated on 36 bits—AD[31:0] signals plus
C/BE[3:0]#. PAR is always calculated on 36 bits, regardless of the valid byte enables. PAR is only guaranteed to
be valid one PCI clock after the corresponding address or data phase.
8.2.3. PCI ARBITRATION
PIIX4 requests the use of the PCI Bus on behalf of ISA devices (bus masters and DMA), IDE DMA slave
devices, and the USB Host Controller using the PHOLD# and PHLDA# signals. These signals connect to the
Host-to-PCI Bridge where the PCI arbiter is located.
ISA devices (Bus Master or DMA) assert DREQ to gain access to the ISA Bus. In response, PIIX4 asserts
PHOLD#. PIIX4 keeps DACK negated until PIIX4 has ownership of the PCI Bus and Memory. The PCI arbiter
asserts PHLDA# to PIIX4 when the above conditions are met. PIIX4 gives ownership of the ISA Bus (PCI and
Memory) to the ISA device after sampling PHLDA# asserted.
The USB Host Controller utilizes the arbitration advantage available through the PHOLD#/PHLDA# protocol to
do multiple transactions on the PCI bus once it has the ownership of the bus and the MLT count has not expired.
The USBHC relinquishes the bus ownership as soon as the transactions are completed or the MLT counter has
expired, whichever happens first.
PIIX4 uses the delay transaction (or delay completion) and passive release features to help raise the available
bandwidth of the PCI bus.
PRELIMINARY
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