82371AB Datasheet, PDF (149/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Bit
Description
0 Host Busy (HOST_BUSY)—RO. 1=Indicates that the SMBus controller host interface is in the
process of completing a command. 0=SMBus controller host interface is not processing a command.
None of the other registers should be accessed if this bit is set.
7.3.2. SMBSLVSTS—SMBUS SLAVE STATUS REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (01h)
00h
Read/Write
This register provides status information concerning the SMBus controller slave interface.
Bit
Description
7:6 Reserved.
5 Alert Status (ALERT_STS)—R/WC. 1=Indicates that the source of SMBus interrupt or resume
event was the assertion of the SMBALERT# signal. 0=SMBus interrupt not caused by SMBALERT#
signal. Setting of this bit requires that the ALERT_EN bit be set. This bit is only set by hardware and
can only be reset by writing a 1 to this bit position.
4 Shadow2 Status (SHDW2_STS)—R/WC. 1=Indicates that the source of SMBus interrupt or resume
event was a slave cycle address match of the SMBSHDW2 port. 0=SMBus interrupt not caused by
address match to SMBSHDW2 port. This bit is only set by hardware and can only be reset by writing
a 1 to this bit position.
3 Shadow1 Status (SHDW1_STS)—R/WC. 1=Indicates that the source of SMBus interrupt or resume
event was a slave cycle address match of the SMBSHDW1 port. 0=SMBus interrupt not caused by
address match to SMBSHDW1 port. This bit is only set by hardware and can only be reset by writing
a 1 to this bit position.
2 Slave Status (SLV_STS)—R/WC. 1=Indicates that the source of SMBus interrupt or resume event
was a slave cycle event match of the SMBSLVC (command match) and SMBSLVEVT
(data event match). 0=SMBus interrupt not caused by slave event match. This bit is only set by
hardware and can only be reset by writing a 1 to this bit position.
1 Reserved.
0 Slave Busy (SLV_BSY)—RO. 1=Indicates that the SMBus controller slave interface is in the
process of receiving data. 0=SMBus controller slave interface is not processing data. None of the
other registers should be accessed if this bit is set.
PRELIMINARY
149
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)