82371AB Datasheet, PDF (180/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
8.8. Timer/Counters
PIIX4 contains three counters that are equivalent to those found in the 82C54 programmable interval timer. The
three counters are contained in one PIIX4 timer unit, referred to as Timer-1. Each counter output provides a key
system function. Counter 0 is connected to interrupt controller IRQ0 and provides a system timer interrupt for a
time-of-day, diskette time-out, or other system timing functions. Counter 1 generates a refresh request signal
and Counter 2 generates the tone for the speaker. The 14.31818-MHz counters normally use OSC as a clock
source.
Counter 0, System Timer
This counter functions as the system timer by controlling the state of IRQ0 and is typically programmed for Mode
3 operation. The counter produces a square wave with a period equal to the product of the counter period (838
ns) and the initial count value. The counter loads the initial count value one counter period after software writes
the count value to the counter I/O address. The counter initially asserts IRQ0 and decrements the count value by
two each counter period. The counter negates IRQ0 when the count value reaches 0. It then reloads the initial
count value and again decrements the initial count value by two each counter period. The counter then asserts
IRQ0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting
and negating IRQ0.
Counter 1, Refresh Request Signal
This counter provides the refresh request signal and is typically programmed for Mode 2 operation. The counter
negates refresh request for one counter period (838 ns) during each count cycle. The initial count value is loaded
one counter period after being written to the counter I/O address. The counter initially asserts refresh request,
and negates it for one counter period when the count value reaches 1. The counter then asserts refresh request
and continues counting from the initial count value.
Counter 2, Speaker Tone
This counter provides the speaker tone and is typically programmed for Mode 3 operation. The counter provides
a speaker frequency equal to the counter clock frequency (1.193 MHz) divided by the initial count value. The
speaker must be enabled by a write to port 061h (see NMI Status and Control ports).
8.8.1. PROGRAMMING THE INTERVAL TIMER
The counter/timers are programmed by I/O accesses and are addressed as though they are contained in one
82C54 interval timer. A single Control Word Register controls the operation of all three counters. The interval
timer is an I/O-mapped device. Several commands are available:
The Control Word Command specifies:
• which counter to read or write
• the operating mode
• the count format (binary or BCD)
The Counter Latch Command latches the current count so that it can be read by the system. The countdown
process continues. The Read Back Command reads the count value, programmed mode, the current state of the
OUT pins, and the state of the Null Count Flag of the selected counter.
The Read/Write Logic selects the Control Word Register during an I/O write when address lines A[1:0]=11. This
condition occurs during an I/O write to port address 043h, the address for the Control Word Register on Timer 1.
If the CPU writes to port 043h, the data is stored in the Control Word Register and is interpreted as the Control
Word used to define the operation of the Counters.
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