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82371AB Datasheet, PDF (5/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4 | |||
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E
82371AB (PIIX4)
4.1.6. CLASSCâClass Code Register (Function 0) .....................................................................................56
4.1.7. HEDTâHeader Type Register (Function 0)........................................................................................56
4.1.8. IORTâISA I/O Recovery Timer Register (Function 0) .......................................................................56
4.1.9. XBCSâX-Bus Chip Select Register (Function 0) ...............................................................................57
4.1.10. PIRQRC[A:D]âPIRQX Route Control Registers (Function 0) .........................................................59
4.1.11. SERIRQCâSerial IRQ Control Register (Function 0) ......................................................................59
4.1.12. TOMâTop of Memory Register (Function 0) ....................................................................................60
4.1.13. MSTATâMiscellaneous Status Register (Function 0)......................................................................61
4.1.14. MBDMA[1:0]âMotherboard Device DMA Control Registers (Function 0)........................................61
4.1.15. APICBASEâAPIC Base Address Relocation Register (Function 0)................................................62
4.1.16. DLCâDeterministic Latency Control Register (Function 0)..............................................................62
4.1.17. PDMACFGâPCI DMA Configuration Register (Function 0).............................................................63
4.1.18. DDMABPâDistributed DMA Slave Base Pointer Registers (Function 0).........................................64
4.1.19. GENCFGâGeneral Configuration Register (Function 0) .................................................................65
4.1.20. RTCCFGâReal Time Clock Configuration Register (Function 0) ....................................................67
4.2. PCI to ISA/EIO Bridge IO Space Registers (IO) ........................................................................................68
4.2.1. DMA Registers.....................................................................................................................................68
4.2.1.1. DCOMâDMA Command Register (IO)........................................................................................68
4.2.1.2. DCMâDMA Channel Mode Register (IO)....................................................................................69
4.2.1.3. DRâDMA Request Register (IO).................................................................................................70
4.2.1.4. WSMBâWrite Single Mask Bit (IO) .............................................................................................70
4.2.1.5. RWAMBâRead/Write All Mask Bits (IO) .....................................................................................71
4.2.1.6. DSâDMA Status Register (IO) ....................................................................................................71
4.2.1.7. DBADDRâDMA Base and Current Address Registers (IO) .......................................................72
4.2.1.8. DBCNTâDMA Base and Current Count Registers (IO)..............................................................72
4.2.1.9. DLPAGEâDMA Low Page Registers (IO)...................................................................................73
4.2.1.10. DCBPâDMA Clear Byte Pointer Register (IO)..........................................................................73
4.2.1.11. DMCâDMA Master Clear Register (IO) ....................................................................................73
4.2.1.12. DCLMâDMA Clear Mask Register (IO).....................................................................................74
4.2.2. Interrupt Controller Registers...............................................................................................................74
4.2.2.1. ICW1âInitialization Command Word 1 Register (IO) ..................................................................74
4.2.2.2. ICW2âInitialization Command Word 2 Register (IO) ..................................................................75
4.2.2.3. ICW3âInitialization Command Word 3 Register (IO) ..................................................................75
4.2.2.4. ICW3âInitialization Command Word 3 Register (IO) ..................................................................76
4.2.2.5. ICW4âInitialization Command Word 4 Register (IO) ..................................................................76
4.2.2.6. OCW1âOperational Control Word 1 Register (IO)......................................................................77
4.2.2.7. OCW2âOperational Control Word 2 Register (IO)......................................................................77
4.2.2.8. OCW3â Operational Control Word 3 Register (IO).....................................................................78
4.2.2.9. ELCR1âEdge/Level Control Register (IO) ..................................................................................79
4.2.2.10. ELCR2âEdge/Level Control Register (IO) ................................................................................79
4.2.3. Counter/Timer Registers......................................................................................................................80
4.2.3.1. TCWâTimer Control Word Register (IO).....................................................................................80
4.2.3.2. TMRSTSâTimer Status Registers (IO) .......................................................................................82
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
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