82371AB Datasheet, PDF (64/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Bit
Description
7:6 DMA CH 3 Select. This field defines the type of DMA performed on this channel.
Bits[7:6]
DMA Type
00
Normal ISA DMA (default)
01
PC/PCI DMA
10
Distributed DMA
11
Reserved
5:4 DMA CH 2 Select. This field defines the type of DMA performed on this channel.
Bits[5:4]
00
01
10
11
DMA Type
Normal ISA DMA (default)
PC/PCI DMA
Distributed DMA
Reserved
3:2 DMA CH 1 Select. This field defines the type of DMA performed on this channel.
Bits[3:2]
DMA Type
00
Normal ISA DMA (default)
01
PC/PCI DMA
10
Distributed DMA
11
Reserved
1:0 DMA CH 0 Select. This field defines the type of DMA performed on this channel.
Bits[1:0]
00
01
10
11
DMA Type
Normal ISA DMA (default)
PC/PCI DMA
Distributed DMA
Reserved
4.1.18. DDMABP—DISTRIBUTED DMA SLAVE BASE POINTER REGISTERS (FUNCTION 0)
Address Offset:
Default Value:
Attribute:
92–93h (CH0-3); 94–95h (CH5-7)
0000h
Read/Write
These registers provide the base address for distributed DMA slave channel registers, one for each DMA
controller. Bits 5:0 are reserved to provide access to a 64-byte IO space (16 bytes per channel). The channels
are accessed using offset from base address as follows (Note that Channel 4 is reserved and is not accessible).
Base Offset
00–0Fh
10–1Fh
20–2Fh
30–3Fh
Channel
0,4
1,5
2,6
3,7
Bit
15:6
5:0
64
Description
Base Pointer. IO Address pointer to DMA Slave Channel registers. Corresponds to PCI address
AD[15:6].
Reserved. Read as 0.
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)