82371AB Datasheet, PDF (161/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Read Transfers
Read transfers move data from ISA memory or the system DRAM, to an ISA I/O device. PIIX4 activates the
IOW# command and the appropriate DRAM and ISA Memory control signals to indicate a memory read. Data
steering is used to steer the data to the correct byte lane during these DMA transfers. When the cycle involves
DRAM, the PCI read transaction is initiated as soon as the DMA address is valid. When the memory is located
on the ISA Bus, a PCI cycle is not initiated.
Verify Transfer
Verify transfers are pseudo transfers. The DMA controller generates addresses as in normal read or write
transfers. However, PIIX4 does not activate the ISA memory and I/O control lines. Only the DACK lines will go
active. PIIX4 asserts the appropriate DACK signal for nine SYSCLKs. If Verify transfers are repeated during
Block or Demand DMA requests, each additional pseudo transfer will add eight SYSCLKs. The DACK lines will
not be toggled for repeated transfers.
NOTE
Verify transfers are not supported with type F DMA.
8.4.3. DMA TIMINGS
ISA-Compatible timing is provided for ISA DMA slave devices that reside on add in cards. In addition, Type F
timing (three SYSCLK period) is provided for motherboard DMA slave and ISA DMA slaves. The Type F timing
(along with the 4-byte DMA buffer) is enabled by setting the MBDMAx[FAST] bit.
The repetition rate for ISA-Compatible DMA cycles is eight SYSCLK periods.
The type F cycles occur back to back at a minimum repetition rate of three SYSCLKs (360 ns min). The type F
cycles are always performed using the 4-byte DMA buffer.
When PIIX4 negates PHOLD# one clock after driving FRAME# asserted for a bus master IDE transaction or a
type F DMA transaction, and another transaction is pending which will cause PIIX4 to acquire the PCI bus, it will
drive PHOLD# asserted for the next transaction three clocks after TRDY# is driven negated for the current
transaction.
8.4.4. DMA BUFFER FOR TYPE F TRANSFERS
The DMA buffer referred to above is a 4-byte buffer that is used to reduce the PCI utilization resulting from DMA
transfers by motherboard devices. The DMA buffer is always used in conjunction with the type F transfers. The
type F transfers and the use of the DMA buffer are invoked by setting the MBDMAx[FAST] register bit for the
appropriate channel. The 4-byte buffer and the type F timings may be used only when the DMA channel is
programmed to increment mode (not decrement), and cannot be used when the channel is programmed to
operate in block mode (single transfer mode and demand mode are legal).
8.4.5. DREQ AND DACK# LATENCY CONTROL
The PIIX4 DMA arbiter maintains a minimum DREQ to DACK# latency on all DMA channels when programmed
in compatible mode. This is to support older devices such as the 8272A. The DREQs are delayed by eight
SYSCLKs prior to being seen by the arbiter logic. This delay guarantees a minimum 1 µsec DREQ to DACK#
latency. Software requests will not have this minimum request to DACK# latency. When programmed to operate
in type F timing mode (by setting MBDMA[FAST]), the eight SYSCLK latency is not
in effect.
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
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(until publication date)