82371AB Datasheet, PDF (16/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
2.1. PIIX4 Signals
2.1.1. PCI BUS INTERFACE
Name
AD[31:0]
C/BE#[3:0]
CLKRUN#
DEVSEL#
FRAME#
16
Type
Description
I/O PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During the first
clock of a transaction, AD[31:0] contain a physical byte address (32 bits). During
subsequent clocks, AD[31:0] contain data.
A PIIX4 Bus transaction consists of an address phase followed by one or more data
phases. Little-endian byte ordering is used. AD[7:0] define the least significant byte
(LSB) and AD[31:24] the most significant byte (MSB).
When PIIX4 is a Target, AD[31:0] are inputs during the address phase of a transaction.
During the following data phase(s), PIIX4 may be asked to supply data on AD[31:0] for
a PCI read, or accept data for a PCI write.
As an Initiator, PIIX4 drives a valid address on AD[31:2] and 0 on AD[1:0] during the
address phase, and drives write or latches read data on AD[31:0] during the data
phase.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
I/O BUS COMMAND AND BYTE ENABLES. The command and byte enable signals are
multiplexed on the same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used as
Byte Enables. The Byte Enables determine which byte lanes carry meaningful data.
C/BE0# applies to byte 0, C/BE1# to byte 1, etc. PIIX4 drives C/BE[3:0]# as an Initiator
and monitors C/BE[3:0]# as a Target.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
I/O CLOCK RUN#. This signal is used to communicate to PCI peripherals that the PCI
clock will be stopped. Peripherals can assert CLKRUN# to request that the PCI clock
be restarted or to keep it from stopping. This function follows the protocol described in
the PCI Mobile Design Guide, Revision 1.0.
During Reset: Low
After Reset: Low
During POS: High
I/O DEVICE SELECT. PIIX4 asserts DEVSEL# to claim a PCI transaction through positive
decoding or subtractive decoding (if enabled). As an output, PIIX4 asserts DEVSEL#
when it samples IDSEL active in configuration cycles to PIIX4 configuration registers.
PIIX4 also asserts DEVSEL# when an internal PIIX4 address is decoded or when PIIX4
subtractively or positively decodes a cycle for the ISA/EIO bus or IDE device. As an
input, DEVSEL# indicates the response to a PIIX4 initiated transaction and is also
sampled when deciding whether to subtractively decode the cycle. DEVSEL# is tri-
stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated until driven by
PIIX4 as a target.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
I/O CYCLE FRAME. FRAME# is driven by the current Initiator to indicate the beginning and
duration of an access. While FRAME# is asserted data transfers continue. When
FRAME# is negated the transaction is in the final data phase. FRAME# is an input to
PIIX4 when it is the Target. FRAME# is an output when PIIX4 is the initiator. FRAME#
remains tri-stated until driven by PIIX4 as an Initiator.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)