82371AB Datasheet, PDF (111/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
SWDBG
(Bit 5)
0
0
1
1
Table 16. Run/Stop, Debug Bit Interaction
Run/Stop
(Bit 0)
Operation
0
If executing a command, the Host Controller completes the command and then
stops. The 1.0 ms frame counter is reset and command list execution resumes
from start of frame using the frame list pointer selected by the current value in the
FRNUM register. (While Run/Stop=0, the FRNUM register can be reprogrammed.)
1
Execution of the command list resumes from Start Of Frame using the frame list
pointer selected by the current value in the FRNUM register. The Host Controller
remains running until the Run/Stop bit is cleared (by Software or Hardware).
0
If executing a command, the Host Controller completes the command and then
stops and the 1.0 ms frame counter is frozen at its current value. All status are
preserved. The Host Controller begins execution of the command list from where
it left off when the Run/Stop bit is set.
1
Execution of the command list resumes from where the previous execution
stopped. The Run/Stop bit is set to 0 by the Host Controller when a TD is being
fetched. This causes the Host Controller to stop again after the execution of the
TD (single step). When the Host Controller has completed execution, the
HCHalted bit in the Status Register is set.
6.2.2. USBSTS—USB STATUS REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (02−03h)
0000h
Read/Write Clear
This register indicates pending interrupts and various states of the Host Controller. The status resulting from a
transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by writing a 1
to it.
Bit
Description
15:6 Reserved.
5 HCHalted. The Host Controller sets this bit to 1 after it has stopped executing as a result of the
Run/Stop bit being set to 0, either by software or by the Host Controller hardware (debug mode or an
internal error).
4 Host Controller Process Error. The Host Controller sets this bit to 1 when it detects a fatal error
and indicates that the Host Controller suffered a consistency check failure while processing a
Transfer Descriptor. An example of a consistency check failure would be finding an illegal PID field
while processing the packet header portion of the TD. When this error occurs, the Host Controller
clears the Run/Stop bit in the Command register to prevent further schedule execution. A hardware
interrupt is generated to the system.
3 Host System Error. The Host Controller sets this bit to 1 when a serious error occurs during a host
system access involving the Host Controller module. In a PCI system, conditions that set this bit to 1
include PCI Parity error, PCI Master Abort, and PCI Target Abort. When this error occurs, the Host
Controller clears the Run/Stop bit in the Command register to prevent further execution of the
scheduled TDs. A hardware interrupt is generated to the system.
PRELIMINARY
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