82371AB Datasheet, PDF (208/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Throttle
Clocks
STPCLK#
Stop Grant
Clocks
STPCLK#
Stop Clock
Clocks
STPCLK#
Programmable Duty Cycle
244 µs Throttle
Slow Burst
Fast Burst
Software
(OS or APM)
Break
Event
Burst
Timer
Expires
The Clock Control Unit Remains in the
Enabled mode until Software breaks it out
Figure 12. Clock Control Mechanisms (with BURST Enabled)
clk_cnt2
11.2.2. STOP CLOCK AND DEEP SLEEP STATE EXAMPLE SEQUENCE
The Stop Clock Mode requires special consideration to allow the processor PLL to stabilize before starting any
activity that would require the processor to snoop its internal cache. The following is an example of system
transition into and out of Stop Clock. Figure 13 shows an example timing diagram. The numbers shown in braces
{} below correspond to the numbers shown in Figure 13.
Entering the processor Stop Clock State:
• Software sets PIIX4 for the appropriate Clock Control Mechanism.
• Software disables the PCI arbiter in the Host Bridge.
• Software sets PIIX4 to enable the Stop Clock Mode by reading LVL3 Register.
• PIIX4 asserts STPCLK# pin.
• Processor accepts STPCLK# interrupt, flushes buffers, sends the STOP GRANT bus cycle.
• The Host Bridge forwards Stop Grant bus cycle to PCI bus and does PCI Master Abort.
• The Host bridge completes the Stop Grant bus cycle by returning an RDY# (BRDY#) to the processor.
• Processor gates the internal clocks to the processor core and enters the Stop Grant state. PIIX4 asserts the
ZZ pin to the SRAM if the [ZZ_EN] bit is set.
208
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)