82371AB Datasheet, PDF (267/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

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82371AB (PIIX4)
SMBHSTCNT, SMBHSTCMD, SMBHSTADD, SMBHSTDAT0, SMBHSTDAT1, and SMBBLKDAT registers
should not be accessed after setting the START bit while the HOST_BUSY bit is active (until completion of
transaction).
The SMBus controller will not respond to the START bit being set unless all interrupt status bits in the
SMBHSTSTS register have been cleared.
For Block Read or Block Write protocols, the data is stored in a 32-byte block data storage array. This array is
addressed via an internal index pointer. The index pointer is initialized to zero on each read of the SMBHSTCNT
register. After each access to the SMBBLKDAT register, the index pointer is incremented by one. For Block
Write transactions, the data to be transferred is stored in this array and the byte count is stored in
SMBHSTDAT0 register prior to initiating the transaction. For Block Read transactions, the SMBus peripheral
determines the amount of data transferred. After the transaction completes, the byte count transferred is located
in SMBHSTDAT0 register and data is stored in the block data storage array. Accesses to the array during
execution of the SMBus transaction always start at address 0.
Any register values needed for computation purposes should be saved prior to the starting of a new transaction,
as the SMBus host controller updates the registers while executing the new transaction.
11.5.4.2.
SMBus Slave Interface
PIIX4 supports three separate mechanisms for SMBus peripherals to communicate to PIIX4. In addition to
transferring data, these mechanisms can generate an interrupt or resume the system from a suspend state.
The first mechanism consists of accesses to the SMBus controller host slave port at address 10h. (Note this
address is actually 0001 000x as this is a 7-bit address (bits[7:1]) with bit 0 being R/W bit.) The host slave port
responds to Word Write transactions only with the incoming data being stored in the SMBSLVDAT register and
incoming command in the SMBSHDWCMD register. An interrupt or resume event is generated
(if enabled) if the incoming command matches the command stored in SMBSLVC register and at least one bit
read into the SMBSLVDAT register matches with the corresponding bit in the SMBSLVEVT register.
The second mechanism monitors for accesses to the SMBus controller slave shadow ports at addresses stored
in SMBSHDW1 and SMBSHDW2 registers. The shadow slave ports responds to Word Write transactions only
with the incoming data being stored in the SMBSLVDAT register and incoming command being stored in the
SMBSHDWCMD register. An interrupt or resume event is generated (if enabled) when the slave shadow ports
are accessed.
The SLV_BSY bit indicates that the PIIX4 slave interface is receiving an incoming message. The SMBSLVCNT,
SMBSHDWCMD, SMBSLVEVT, SMBSLVDAT, and SMBSLVC registers should not be accessed while the
SLV_BSY bit is active (until completion of transaction).
The third method for SMBus devices to communicate with PIIX4 is with the SMBALERT# signal. When enabled
and the SMBALERT# signal is asserted, PIIX4 generates an interrupt or resume the system from a suspend
state. This simple mechanism allows a device without SMBus master capabilities to request service from the
SMBus host (PIIX4). To determine which device asserted the SMBALERT# signal, the PIIX4 host controller
should be programmed to execute a read command using the Alert Response Address.
Once the slave interface has received a transaction and generated an interrupt, it will stop responding to new
requests until all the interrupt status bits in the SMBSLVSTS register are cleared.
PRELIMINARY
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