82371AB Datasheet, PDF (277/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
14.0. TESTABILITY
14.1. Test Mode Description
PIIX4 supports two types of test modes, a tri-state test mode and a NAND tree test mode. Table 58 lists IRQ
decodes necessary to enter each test mode. The test modes are decoded from the IRQ inputs (IRQ[7:3]) and
qualified with the TEST# pin.
Table 58. Test Mode Selection
Test Mode
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
TEST#
No Test Mode Selected
0
0
0
0
0
0
NAND Tree 1
0
0
0
0
1
0
NAND Tree 2
0
0
0
1
0
0
NAND Tree 3
0
0
0
1
1
0
NAND Tree 4
0
0
1
0
0
0
NAND Tree 5
0
0
1
0
1
0
All NAND Trees
1
1
1
1
1
0
Tri-state All Outputs
0
1
0
0
1
0
The entry into a test mode is shown in Figure 37. Each test mode entry sequence is characterized by two active
low pulses on the test pin. During the first active low pulse the desired test mode should be driven onto the IRQ
lines. The test mode is latched into PIIX4 on the rising edge of the first TEST# pulse. The test mode is actually
entered upon the rising edge of the second active low TEST# pulse. To change test modes, the same sequence
should be followed again. To restore the PIIX4 to normal operation, execute the sequence with IRQ[7:3]=00000
(No Test Mode Selected).
RSMRST#
PWROK
TEST#
Test Mode Entered
IRQ[7:3]
Test Mode
Other Signal Outputs
All Output Signals Tri-Stated
NAND Tree
Output Enabled
testmode
Figure 37. Test Mode Entry (NAND Tree Example)
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