82371AB Datasheet, PDF (23/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
2.1.4. DMA SIGNALS
Name
DACK[0,1,2,3]#
DACK[5,6,7]#
DREQ[0,1,2,3]
DREQ[5,6,7]
REQ[A:C]#/
GPI[2:4]
GNT[A:C]#/
GPO[9:11]
TC
Type
O
I
I
O
O
Description
DMA ACKNOWLEDGE. The DACK# output lines indicate that a request for DMA
service has been granted by PIIX4 or that a 16-bit master has been granted the
bus. The active level (high or low) is programmed via the DMA Command
Register. These lines should be used to decode the DMA slave device with the
IOR# or IOW# line to indicate selection. If used to signal acceptance of a bus
master request, this signal indicates when it is legal to assert MASTER#. If the
DREQ goes inactive prior to DACK# being asserted,
the DACK# signal will not be asserted.
During Reset: High
After Reset: High
During POS: High
DMA REQUEST. The DREQ lines are used to request DMA service from PIIX4’s
DMA controller or for a 16-bit master to gain control of the ISA expansion bus. The
active level (high or low) is programmed via the DMA Command Register. All
inactive to active edges of DREQ are assumed to be asynchronous. The request
must remain active until the appropriate DACKx# signal is asserted.
PC/PCI DMA REQUEST. These signals are the DMA requests for PC/PCI
protocol. They are used by a PCI agent to request DMA services and follow the
PCI Expansion Channel Passing protocol as defined in the PCI DMA section.
If the PC/PCI request is not needed, these pins can be used as general-purpose
inputs.
PC/PCI DMA ACKNOWLEDGE. These signals are the DMA grants for PC/PCI
protocol. They are used by a PIIX4 to acknowledge DMA services and follow the
PCI Expansion Channel Passing protocol as defined in the PCI DMA section.
If the PC/PCI request is not needed, these pins can be used as general-purpose
outputs.
During Reset: High
After Reset: High
During POS: High/GPO
TERMINAL COUNT. PIIX4 asserts TC to DMA slaves as a terminal count
indicator. PIIX4 asserts TC after a new address has been output, if the byte count
expires with that transfer. TC remains asserted until AEN is negated, unless AEN
is negated during an autoinitialization. TC is negated before AEN is negated during
an autoinitialization.
During Reset: Low
After Reset: Low
During POS: Low
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)