82371AB Datasheet, PDF (90/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Bit
Description
3 Special Cycle Enable (Not Implemented). This bit is hardwired to 0.
2 Bus Master Function Enable (BME). 1=Enable. 0=Disable.
1 Memory Space Enable (Not Implemented). This bit is hardwired to 0.
0 I/O Space Enable (IOSE). This bit controls access to the I/O space registers. When IOSE=1,
access to the Legacy IDE ports (both primary and secondary) and the PCI Bus Master IDE I/O
Registers is enabled. The Base Address Register for the PCI Bus Master IDE I/O Registers should
be programmed before this bit is set to 1.
5.1.4. PCISTS—PCI DEVICE STATUS REGISTER (FUNCTION 1)
Address Offset:
Default Value:
Attribute:
06–07h
0280h
Read/Write
PCISTS is a 16-bit status register for the IDE interface function. The register also indicates PIIX4’s DEVSEL#
signal timing.
Bit
Description
15 Detected Parity Error (Not Implemented). Read as 0.
14 SERR# Status (Not Implemented). Read as 0.
13 Master-Abort Status (MAS)—R/WC. When the Bus Master IDE interface function, as a master,
generates a master abort, MAS is set to a 1. Software sets MAS to 0 by writing a 1 to this bit.
12 Received Target-Abort Status (RTA)—R/WC. When the Bus Master IDE interface function is a
master on the PCI Bus and receives a target abort, this bit is set to a 1. Software sets RTA to 0 by
writing a 1 to this bit.
11 Signaled Target Abort Status (STA)—R/WC. This bit is set when the PIIX4 IDE interface function
is targeted with a transaction that PIIX4 terminates with a target abort. Software resets STA to 0 by
writing a 1 to this bit.
10:9 DEVSEL# Timing Status (DEVT)—RO. For PIIX4, DEVT=01 indicating medium timing for
DEVSEL# assertion when performing a positive decode. DEVSEL# timing does not include
configuration cycles.
8 Data Parity Detected (DPD) (Not Implemented). Read as 0.
7 Fast Back to back Capable (FBC)—RO. Hardwired to 1. This bit indicates to the PCI Master that
PIIX4 as a target, is capable of accepting fast back-to-back transactions.
6:0 Reserved. Read as 0’s.
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(until publication date)