82371AB Datasheet, PDF (133/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
7.1.23. DEVRESH—DEVICE RESOURCE H (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
74–77h
00h
Read/Write
Bit
Description
31:15
Memory Decode Base Address (MBASE_DEV13)—R/W. Specifies the 17-bit memory base
address range (AD[31:15]) for the device 13 memory range. When this field is combined with the
MMASK_DEV13 field, a memory range is defined from the base address value to the size defined by
the mask register.
14:8 Reserved.
7 Device 13 Memory Monitor Enable (MEM_EN_DEV13)—R/W. 1=Enable PCI bus decode for
accesses to the memory address range selected by the MBASE_DEV13 and MMASK_DEV13
fields. 0=Disable. The EIO enable bit or trap enable bit for device 13 must also be set in order to
enable these respective functions.
6:0 Memory Decode Mask (MMASK_DEV13)—R/W. Specifies the 7-bit memory base address mask
used to determine the memory address range size for device 13 accesses. MMASK_DEV13
(bits[6:0]) correspond to AD[21:15]. A ‘1’ in a bit position indicates that the corresponding address bit
is masked (i.e. ignored) when performing the decode. Note that programming these bits to certain
patterns (such as ‘1110011’) results in split address ranges.
7.1.24. DEVRESI—DEVICE RESOURCE I (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
78–7Bh
00h
Read/Write
Bit
Description
31:21 Reserved.
20 Generic I/O Decode 0 Enable (IO_EN_GDEC0)—R/W. 1=Enable accesses to the I/O address
range selected by the IO_MASK_GDEC0 and IO_BASE_GDEC0 fields to be claimed by PIIX4 and
forwarded to the ISA/EIO bus. 0=Disable.
19:16
Generic Decode 0 I/O Mask (IO_MASK_GDEC0)—R/W. This field specifies the 4-bit I/O base
address mask used to determine the IO address range size. IO_MASK_GDEC0(bits[19:16])
correspond to AD[3:0]. A ‘1’ in a bit position indicates that the corresponding address bit is masked
(i.e., ignored) when performing the decode. Note that programming these bits to certain patterns
(such as 1001) results in a split address range.
15:0 Generic Decode 0 I/O Base Address (IO_BASE_GDEC0)—R/W. Specifies the 16-bit I/O base
address range (AD[15:0]) for the generic decode range 0. When this field is combined with
IO_MASK_GDEC0 field, an I/O range is defined starting from the base address register value to the
size defined by the mask register.
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