82371AB Datasheet, PDF (114/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
6.2.6. SOFMOD—START OF FRAME (SOF) MODIFY REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (0Ch)
40h
Read/Write
This 1-byte register is used to modify the value used in the generation of SOF timing on the USB. Only the seven
least significant bits are used. When a new value is written into these 7 bits, the SOF timing of the next frame will
be adjusted. This feature can be used to adjust out any offset from the clock source that generates the clock that
drives the SOF counter. This register can also be used to maintain real time synchronization with the rest of the
system so that all devices have the same sense of real time. Using this register, the frame length can be
adjusted across the full range required by the USB specification. Its initial programmed value is system
dependent based on the accuracy of hardware USB clock and is initialized by system BIOS. It may be
reprogrammed by USB system software at any time. Its value will take effect from the beginning of the next
frame. This register is reset upon a Host Controller Reset or Global Reset. Software must maintain a copy of its
value for reprogramming if necessary.
Bit
Description
7 Reserved.
6:0 SOF Timing Value. Guidelines for the modification of frame time are contained in Chapter 7 of the
USB Specification. The SOF cycle time (number of SOF counter clock periods to generate a SOF
frame length) is equal to 11,936 + value in this field. The default value is decimal 64 which gives a
SOF cycle time of 12,000. For a 12-MHz SOF counter clock input, this produces a 1-ms Frame
period. The following table indicates what SOF Timing Value to program into this field for
a certain frame period.
Frame Length
(# 12-MHz Clocks)
(decimal)
11,936
11,937
.
.
11,999
12,000
12,001
.
.
12,062
12,063
SOF Reg. Value
(decimal)
0
1
.
.
63
64
65
.
.
126
127
114
PRELIMINARY
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)