82371AB Datasheet, PDF (140/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
E
Bit
Description
8 USB Status (USB_STS)—R/WC. 1=USB interface has indicated that a USB resume has been
driven onto one of the two USB ports while in Power On Suspend. 0=No USB resume has been
detected. If the USB_EN bit is set the setting of the USB_STS bit will generate a resume event. This
bit is only set by hardware and can only be reset by writing a 1 to this bit position.
7 Thermal Override Status (THRMOR_STS)—R/WC. 1=THRM# signal has been asserted LOW and
thermal clock throttling has been initiated. 0=Thermal clock throttling has not been initiated. This bit is
set anytime the thermal state machine generates a thermal override condition and starts throttling the
CPU’s clock at the THRM_DTY ratio. This bit is set by hardware and can only be cleared by writing
a 1 to this bit position.
6:1 Reserved.
0 Thermal Status (THRM_STS)—R/WC. 1=THRM# signal has been asserted. 0=THRM# signal has
not been asserted. Assertion level is dependent upon polarity enable bit THRM_POL. If the
THRM_EN bit is set then the setting of the THRM_STS bit will generate an SCI or SMI. This bit is
only set through hardware and is cleared by writing a 1 to this bit position.
7.2.6. GPEN—GENERAL PURPOSE ENABLE REGISTER (IO)
I/O Address:
Default Value:
Attribute:
Base + (0Eh)
00h
Read/Write
Bit
Description
15:12 Reserved.
11 Lid Enable (LID_EN)—R/W. 1=Enable the generation of an SMI#, SCI, or resume event upon the
setting of the LID_STS bit. 0=Disable.
10 Ring Enable (RI_EN)—R/W. 1=Enable the generation of a resume event upon the setting of the
RI_STS bit. 0=Disable.
9 GPI Enable (GPI_EN)—R/W. 1=Enable the generation of an SMI#, SCI, or resume event upon the
setting of the GPI_STS bit. 0=Disable.
8 USB Enable (USB_EN)—R/W. 1=Enable the generation of a resume event upon the setting of the
USB_STS bit. 0=Disable.
7:1 Reserved.
0 Thermal Enable (THRM_EN)—R/W. 1=Enable the generation of an SMI# or SCI upon the setting of
the THRM_STS bit. 0=Disable.
140
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INTEL CONFIDENTIAL
(until publication date)