82371AB Datasheet, PDF (52/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

82371AB (PIIX4)
Table 11. Power Management I/O Registers
Offset From Mnemonic
Base Address
Register Name
30–33h
34–37h
GPIREG
GPOREG
General Purpose Input
General Purpose Output
NOTES:
1. The base address is programmable via the PMBA Register (40–43h; function 3)
Table 12. System Management Bus (SMBus) I/O Registers
Offset From
Base Address
Mnemonic
Register Name
00h
SMBHSTSTS
SMBus Host Status
01h
SMBSLVSTS
SMBus Slave Status
02h
SMBHSTCNT
SMBus Host Count
03h
SMBHSTCMD SMBus Host Command
04h
SMBHSTADD
SMBus Host Address
05h
SMBHSTDAT0 SMBus Host Data 0
06h
SMBHSTDAT1 SMBus Host Data 1
07h
SMBBLKDAT
SMBus Block Data
08h
SMBSLVCNT
SMBus Slave Count
09h
SMBSHDWCMD SMBus Shadow Command
0A–0Bh
SMBSLVEVT
SMBus Slave Event
0C–0Dh
SMBSLVDAT
SMBus Slave Data
NOTES:
1. The base address is programmable via the SMBBA Register (90–93h; function 3)
E
Access
RO
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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