82371AB Datasheet, PDF (87/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
4.2.7.2.
P92—Port 92 Register (IO)
I/O Address:
Default Value:
Attribute:
92h
00h
Read/Write
Bit
Description
7:2 Reserved. Returns 0 when read.
1 FAST_A20. 1=Causes A20M# signal to be asserted to 0. 0=A20M# signal determined by A20GATE
signal. This signal is internally combined with the A20GATE input signal. The result is then output via
the A20M# signal to the processor for support of real mode compatible software.
The A20GATE signal generated by the keyboard is used in conjunction with the FAST_A20 bit in the
P92 register to generate the A20M# signal that goes to the CPU. The A20M# signal is generated
according to the following table:
Bit 1
0
0
1
1
A20GATE
(Input Signal)
Negated (Low)
Asserted (High)
Negated (Low)
Asserted (High)
A20M#
(Output Signal)
Asserted (Low)
Negated (High)
Negated (High)
Negated (High)
0 FAST_INIT. This read/write bit provides a fast software executed processor reset function. This
function provides an alternate means to reset the system processor to effect a mode switch from
Protected Virtual Address Mode to the Real Address Mode. This provides a faster means of reset
than is provided by the Keyboard controller. Writing a 1 to this bit will cause the INIT signal to pulse
active (high) for approximately 16 PCI Clocks. Before another INIT pulse can be generated via this
register, this bit must be written back to a 0.
4.2.7.3.
CERR—Coprocessor Error Register (IO)
I/O Address:
Default Value:
Attribute:
F0h
N/A
Write only
Writing to this register causes PIIX4 to assert IGNNE#. PIIX4 also negates IRQ13 (internal to PIIX4). Note, that
IGNNE# is not asserted unless FERR# is active. Reads/writes flow through to the ISA Bus.
Bit
Description
7:0 Assert IGNNE#. No special pattern required. A write to address F0h causes assertion of IGNNE# if
FERR# is asserted.
PRELIMINARY
87
4/9/97 2:23 PM PIIX4aDS
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